Datasheet

LIS2DH Digital interfaces
Doc ID 022516 Rev 1 23/49
5 Digital interfaces
The registers embedded inside the LIS2DH may be accessed through both the I
2
C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
2
C interface, CS
line must be tied high (i.e. connected to Vdd_IO).
5.1 I
2
C serial interface
The LIS2DH I
2
C is a bus slave. The I
2
C is employed to write data into registers whose
content can also be read back.
The relevant I
2
C terminology is given in the table below.
There are two signals associated with the I
2
C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistor. When the bus is free both the lines are high.
The I
2
C interface is compliant with fast mode (400 kHz) I
2
C standards as well as with the
Normal mode.
Table 12. Serial interface pin description
Pin name Pin description
CS
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I2C disabled)
SCL
SPC
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SA0
SDO
I
2
C less significant bit of the device address (SA0)
SPI serial data output (SDO)
Table 13. Serial interface pin description
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master