Datasheet

Block diagram and pin description LIS2DH12
8/53 DocID025056 Rev 6
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
CHARGE
AMPLIFIER
Y+
Z+
Y-
Z-
a
X+
X-
I2C
SPI
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
CONTROL LOGIC
&
INTERRUPT GEN.
INT 1
CLOCK
TRIMMING
CIRCUITS
Temperature
SELF TEST
CONTROL
A/D
CONVERTER
INT 2
MUX
32 Level
FIFO
LOGIC
Sensor
AM10218V2
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
Y
1
X
Z
Vdd_IO
SC L/SPC
SDA/SDI/SDO
CS
SDO/SA0
RES
GND
INT1
INT2
RES
Vdd
RES
(BOTTOM VIEW)
Pin 1 indicator
4
1
5
7
11
8
RES
RES
12 14
GND
SC L/SPC
SDA/SDI/SDO
CS
SDO/SA0
GND
RES
INT 1
Vdd_IO
(BOTTOM VIEW)
4
1
5
6
GND
11
INT 2
7
10
Vdd
12