Datasheet
Application hints LIS2DH12
20/53 DocID025056 Rev 6
4 Application hints
Figure 5. LIS2DH12 electrical connections
The device core is supplied through the Vdd line while the I/O pads are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should
be placed as near as possible to pin 9 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd while maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I
2
C or SPI interfaces. When using the I
2
C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I
2
C/SPI interface.
Vdd_IO
Digital signal from/to signal controller. Signal levels are dened by proper selection of Vdd_IO
10μF
Vdd
100nF
GND
RES
SC
L/SPC
SDA/SDI/SDO
CS
SDO/SA0
GND
GND
INT 2
Vdd_IO
4
1
6
5
GND
12
INT 1
7
10
Vdd
100nF
11