Datasheet

DocID022450 Rev 7 25/45
L7986 Application information
45
In Figure 14 the Bode diagram of the PWM and LC filter transfer function [G
PW0
· G
LC
(f)]
and the open-loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEII
(f)] are drawn.
Figure 14. Open-loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R
1
, usually between 1 k Ω and 5 k Ω , in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 29
where f
ESR
is the ESR zero:
Equation 30
and V
S
is the sawtooth amplitude. The voltage feed-forward keeps the ratio V
S
/V
IN
constant.
3. Calculate C
4
by placing the zero one decade below the output filter double pole:
Equation 31
4. Then calculate C
3
in order to place the second pole at four times the system bandwidth
(BW):
Equation 32
R
4
f
ESR
f
LC
----------- -


2
BW
f
ESR
------------
V
S
V
IN
--------- R
1
⋅⋅⋅=
f
ESR
1
2π ESR C
OUT
⋅⋅
--------------------------------------------=
C
4
10
2π R
4
f
LC
⋅⋅
-------------------------------=
C
5
C
4
2π R
4
C
4
4BW⋅ 1–⋅⋅⋅
--------------------------------------------------------------=