Datasheet

Application information L7985
24/44 DocID022446 Rev 8
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G
PW0
· G
LC
(f))
and the open-loop gain (G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEII
(f)) are shown.
Figure 14. Open-loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R
1
, usually between 1 kΩ and 5 kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 29
where f
ESR
is the ESR zero:
Equation 30
and V
S
is the sawtooth amplitude. The voltage feed-forward keeps the ratio V
S
/V
IN
constant.
3. Calculate C
4
by placing the zero one decade below the output filter double pole:
Equation 31
4. Then calculate C
3
in order to place the second pole at four times the system bandwidth
(BW):
R
4
f
ESR
f
LC
----------- -


2
BW
f
ESR
------------
V
S
V
IN
--------- R
1
=
f
ESR
1
2 ESR C
OUT

------------------------------------------- -=
C
4
10
2 R
4
f
LC

-------------------------------=