Datasheet

Electrical characteristics L6386E
8/19 DocID13989 Rev 4
4.3 Timing diagram
Figure 3. Input/output timing diagram
Note: If SD is set low, each output remains in shut-down condition also after the rising edge of SD,
until the first rising edge of the input signal occurs.
)*/
-*/
4%
)065
-065
7
3&'
7
$*/
%*"(
%*/"7