Datasheet

DocID14914 Rev 3 7/17
L6386AD Electrical characteristics
17
3.3 Timing diagram
Figure 3. Input/output timing diagram
(1)
1. If the SD is set low, each output remains in the shutdown condition also after the rising edge of the SD, until the first rising
edge of the input signal occurs.
Symbol Pin Parameter Test condition Min Typ Max Unit
Logic inputs
V
il
1, 2, 3
Low level logic voltage 1.5 V
V
ih
High level logic voltage 3.6 V
I
ih
High level logic input current V
IN
= 15 V 50 70 A
I
il
Low level logic input current V
IN
= 0 V 1 A
Sense comparator
V
io
Input offset voltage -10 10 mV
I
io
6 Input bias current V
CIN
0.5 0.2 A
V
ol
2 Open drain low level output voltage I
od
= -2.5 mA 0.8 V
V
ref
Comparator reference voltage 0.46 0.50 0.54 V
1. R
DS(on)
is tested in the following way:
where I
1
is the pin 14 current when V
BOOT
= V
BOOT1
, I
2
when V
BOOT
= V
BOOT2
.
Table 6. DC operation electrical characteristics (continued) (V
CC
= 15 V; T
J
= 25 °C)
R
DSON
V
CC
V
BOOT1
–V
CC
V
BOOT2
––
I
1
V
CC
,V
BOOT1
I
2
V
CC
,V
BOOT2
–
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