Datasheet

Figure 9 : Open Loop Test Circuit.
Highpeakcurrentsassociatedwith capacitiveloads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5KΩpotentiometerareusedtosamplethe oscillator
waveform and apply an adjustable ramp to pin 3.
Figure 10 : ShutdownTechniques.
Shutdown of the UC2842 can be accomplished by
two methods ; eitherraise pin 3 above1V or pull pin
1 below a voltage two diode drops above ground.
Either method cause the output of the PWM com-
parator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will
remain low until the next clock cycle after the shut-
downconditionat pins1and/or3is removed.In one
example, an externally latched shutdown may be
accomplishedbyadding anSCR which will be reset
bycyclingV
i
belowthelowerUVLOthreshold.Atthis
pointthereferenceturns off,allowing theSCR to re-
set.
UC2842/3/4/5-UC3842/3/4/5
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