Datasheet
DocID2053 Rev 3 9/15
HCF4051 Electrical characteristics
Figure 4. Typical bias voltages
1. The ADDRESS (digital-control inputs) and INHIBIT logic levels are : “0” = V
SS
and “1” = V
DD
. The analog signal (through
the TG) may swing from V
EE
to V
DD.
Special considerations
Control of analog signals up to 20 V peak-to-peak can be achieved by digital signal
amplitudes of 4.5 to 20 V (if V
DD
- V
SS
= 3 V, a V
DD
- V
EE
of up to 13 V can be controlled; for
V
DD
- V
EE
level differences above 13 V, a V
DD
- V
SS
of at least 4.5 V is required).
For example, if V
DD
= +5, V
SS
= 0, and V
EE
= -13.5, analog signals from -13.5 V to 4.5 V can
be controlled by digital inputs of 0 to 4.5 V. In certain applications, the external load resistor
current may include both V
DD
and signal-line components. To avoid drawing V
DD
current
when switch current flows into the transmission gate inputs, the voltage drop across the
bidirectional switch must not exceed 0.8 V (calculated from R
ON
values shown in Table 6:
DC specifications). No V
DD
current flows through R
L
if the switch current flows into lead 3.
Figure 5. Test circuit
1. C
L
= 50 pF or equivalent (includes jig and probe capacitance)
R
L
= 200 KΩ
R
T
= Z
OUT
of pulse generator (typically 50 Ω).
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