User Guide

2 Page EEPROMs cycling strategies
Simple recommendations and good cycling strategy can really optimize the cycling endurance of page EEPROM
products.
As a power-down during a page write cycle can corrupt the whole addressed page, the areas containing the
read-only parameters and the cycled items should be separated and made as much as possible independent from
each other. These two types of data should not share the same pages.
For more information about power loss and data corruption refer to the application note AN5747 (Page EEPROM
memory architecture).
Also, it is recommended to gather data which have the same cycling rates. These gathered data is called data
class in the following cycling strategies.
2.1 Page EEPROM strategy 1: pages counting cycling strategy
The first cycling strategy is monitoring the write endurance of each page with a dedicated counter byte.
With data class and page counter value, if one page reaches the 500k cycles the whole data class should be
relocated to another physically independent memory address.
Example:
In
Figure 2, data class 1 cycles every hour and data class 2 cycles every minute. If one page of Data class 2
reached 500 k cycles, the whole data class (page 3 + page 4) is relocated further in the memory array as show in
Figure 1.
The read only pages and the data classes stay separated.
Figure 2. Page EEPROM pages counting cycling strategy
DT57097V1
500 k cycles :
Data class 2
relocated
Counter byte
Data class 1
Data class 2
Data class 3
Read Only Data
Page 0
Page 1
Page 2
Page 3
Page 8192
AN5866
Page EEPROMs cycling strategies
AN5866 - Rev 1
page 4/14