User Guide

1.2 Cycling qualification method
The qualification cycling pattern is defined to reach three weeks (~ 500 h cycling time) as defined in JEDEC
JESD47. During the qualification phase, the page EEPROM parts are cycled and then read to locate eventual
failing bit. Page EEPROM architecture embeds DMU (data memory unit) as illustrated in the figure below:
Figure 1. M95P32 DMU architecture
DT57096V2
DMU0 DMU1
DMU2 DMU3
In the M95P32, each DMU are cycled from 1% (5 k cycles) to 100% max specification (500 k cycles) with different
erase operations (page erase, sector erase and block erase). DMU are not cycled at the same time to check if
cycling one DMU does not disturb the others. The full content is always verified with a read operation.
1.3 Overall number of cycles
The number of cycles can be defined either for each page or for the overall number of cycles decoded by the
whole memory:
• The max cycling value defined in the datasheet is the max number of cycles for each page: 500 K cycles.
• The overall number of cycles is the maximum number of cycles qualified for the page EEPROM: 1 billion
cycles.
AN5866
Cycling qualification method
AN5866 - Rev 1
page 3/14