Corp. Computer Hardware User Manual

uPSD3212A, uPSD3212C, uPSD3212CV
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Figure 75. Synchronous Clock Mode Timing – PLD
Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t
CLCL
= t
CH
+ t
CL
.
Symbol Parameter Conditions Min Max
PT
Aloc
Turbo
Off
Slew
rate
(1)
Unit
f
MAX
Maximum Frequency
External Feedback
1/(t
S
+t
CO
)
40.0 MHz
Maximum Frequency
Internal Feedback (f
CNT
)
1/(t
S
+t
CO
–10)
66.6 MHz
Maximum Frequency
Pipelined Data
1/(t
CH
+t
CL
)
83.3 MHz
t
S
Input Setup Time 12 + 2 + 10 ns
t
H
Input Hold Time 0 ns
t
CH
Clock High Time Clock Input 6 ns
t
CL
Clock Low Time Clock Input 6 ns
t
CO
Clock to Output Delay Clock Input 13 – 2 ns
t
ARD
CPLD Array Delay
Any
macrocell
11 + 2 ns
t
MIN
Minimum Clock Period
(2)
t
CH
+t
CL
12 ns
t
CH
t
CL
t
CO
t
H
t
S
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
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