Corp. Computer Hardware User Manual

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1/163December 2004

uPSD3212A, uPSD3212C

uPSD3212CV

Flash Programmable System Devices with

8032 MCU with USB and Programmable Logic

FEATURES SUMMARY

■ FAST 8-BIT 8032 MCU

– 40MHz at 5.0V, 24MHz at 3.3V

– Core, 12-clocks per instruction

■ DUAL FLASH MEMORIES WITH MEMORY

MANAGEMENT

– Place either memory into 8032 program

address space or data address space

– READ-while-WRITE operation for In-

Application Programming and EEPROM

emulation

– Single voltage program and erase

– 100K minimum erase cycles, 15-year

retention

■ CLOCK, RESET, AND SUPPLY

MANAGEMENT

– SRAM is Battery Backup capable

– Normal, Idle, and Power Down Modes

– Power-on and Low Voltage reset

supervisor

– Programmable Watchdog Timer

■ PROGRAMMABLE LOGIC, GENERAL

PURPOSE

– 16 macrocells

– Implements state machines, glue-logic,

and so forth

■ COMMUNICATION INTERFACES

–I

C Master/Slave bus controller

– Two UARTs with independent baud rate

– Six I/O ports with up to 46 I/O pins

– 8032 Address/Data bus available on

TQFP80 package

– 5 PWM outputs, 8-bit resolution

– USB v1.1, low-speed 1.5Mbps, 3

endpoints (uPSD3212A only)

Figure 1. Packages

■ JTAG IN-SYSTEM PROGRAMMING

– Program the entire device in as little as

10 seconds

■ A/D CONVERTER

– Four channels, 8-bit resolution, 10µs

■ TIMERS AND INTERRUPTS

– Three 8032 standard 16-bit timers

– 10 Interrupt sources with two external

interrupt pins

■ Single Supply Voltage

– 4.5 to 5.5V

– 3.0 to 3.6V

TQFP52 (T)

52-lead, Thin,

Quad, Flat

TQFP80 (U)

80-lead, Thin,

Quad, Flat

www.BDTIC.com/ST

Summary of content (163 pages)

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uPSD3212A, uPSD3212C uPSD3212CV Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic FEATURES SUMMARY ■ ■ ■ FAST 8-BIT 8032 MCU – 40MHz at 5.0V, 24MHz at 3.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 1. Device Summary Max 1st 2nd SRAM Clock Flash Flash GPIO (bytes) (MHz) (bytes) (bytes) Part Number USB 8032 Bus VCC (V) Pkg. Temp. uPSD3212C-40T6 40 64K 16K 2K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C uPSD3212CV-24T6 24 64K 16K 2K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C uPSD3212C-40U6 40 64K 16K 2K 46 No Yes 4.5-5.5 TQFP80 –40°C to 85°C uPSD3212CV-24U6 24 64K 16K 2K 46 No Yes 3.0-3.
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uPSD3212A, uPSD3212C, uPSD3212CV TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 52-PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARCHITECTURE OVERVIEW . . . . . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PORT Type and Description . . . . . . . . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 92 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV SUMMARY DESCRIPTION The uPSD321x Series combines a fast 8051based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix including USB, to form an ideal embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz. A JTAG serial interface is used for In-System Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The USB 1.
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uPSD3212A, uPSD3212C, uPSD3212CV 40 P1.6/ADC2 41 P1.7/ADC3 42 PB7 43 PB6 44 RESET_ 45 GND 46 VREF 47 PB5 48 PB4 49 PB3 50 PB2 51 PB1 52 PB0 Figure 3. TQFP52 Connections PD1/CLKIN 1 39 P1.5/ADC1 PC7 2 38 P1.4/ADC0 JTAG TDO 3 37 P1.3/TXD1 JTAG TDI 4 USB–(1) 5 36 P1.2/RXD1 35 P1.1/T2X PC4/TERR_ 6 34 P1.0/T2 VCC 8 33 VCC 32 XTAL2 GND 9 31 XTAL1 USB+ 7 PC3/TSTAT 10 30 P3.7/SCL1 PC2/VSTBY 11 29 P3.6/SDA1 P3.3/EXINT1 26 P3.2/EXINT0 25 P3.1/TXD 24 P3.0/RXD 23 P4.0 22 P4.
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uPSD3212A, uPSD3212C, uPSD3212CV 61 P1.6/ADC2 62 WR_ 63 PSEN_ 64 P1.7/ADC3 65 RD_ 66 PB7 67 PB6 68 RESET_ 70 VREF 69 GND 72 PB5 71 NC(2) 73 PB4 74 PB3 75 P3.0/RXD0 76 PB2 77 P3.1/TXD0 78 PB1 79 P3.2/EXINT0 80 PB0 Figure 4. TQFP80 Connections PD2 1 60 P1.5/ADC1 P3.3 /EXINT1 2 59 P1.4/ADC0 PD1/CLKIN 3 58 P1.3/TXD1 ALE 4 57 A11 PC7 5 56 P1.2/RXD1 JTAG/TDO 6 55 A10 54 P1.1/TX2 JTAG/TDI 7 USB–(1) 8 53 A9 PC4/TERR_ 9 52 P1.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 2. 80-Pin Package Pin Description Function Signal Name Pin No.
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uPSD3212A, uPSD3212C, uPSD3212CV Function Signal Name Pin No. P4.4 PWM1 25 I/O General I/O port pin 8-bit Pulse Width Modulation output 1 P4.5 PWM2 23 I/O General I/O port pin 8-bit Pulse Width Modulation output 2 P4.6 PWM3 19 I/O General I/O port pin 8-bit Pulse Width Modulation output 3 P4.7 PWM4 18 I/O General I/O port pin Programmable 8-bit Pulse Width modulation output 4 USB– 8 I/O Pull-up resistor required (2kΩ for 3V devices, 7.
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uPSD3212A, uPSD3212C, uPSD3212CV Function Signal Name Pin No. JTAG TMS 20 I JTAG pin JTAG TCK 16 I JTAG pin PC2 VSTBY 15 I/O General I/O port pin PC3 TSTAT 14 I/O General I/O port pin PC4 TERR_ 9 I/O General I/O port pin 4. JTAG TDI 7 I JTAG pin 5. JTAG TDO 6 O JTAG pin 5 I/O General I/O port pin 3 I/O General I/O port pin 1. 2. PLD I/O Clock input to PLD and APD PD2 1 I/O General I/O port pin 1. 2.
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uPSD3212A, uPSD3212C, uPSD3212CV ARCHITECTURE OVERVIEW Memory Organization The uPSD321x Devices’s standard 8032 Core has separate 64KB address spaces for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space. The Flash memory consists of two flash memory blocks: the main Flash (512Kbit) and the Secondary Flash (128Kbit).
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uPSD3212A, uPSD3212C, uPSD3212CV Registers The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register). Accumulator. The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown in Figure 6.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 9. PSW (Program Status Word) Register MSB PSW CY AC FO RS1 RS0 OV Carry Flag LSB P Reset Value 00h Parity Flag Auxillary Carry Flag Bit not assigned General Purpose Flag Overflow Flag Register Bank Select Flags (to select Bank0-3) AI06639 Program Memory The program memory consists of two Flash memory: 64KByte Main Flash and 16KByte of Secondary Flash. The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool.
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uPSD3212A, uPSD3212C, uPSD3212CV SFR The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15., page 28 gives an overview of the Special Function Registers. Sixteen address in the SFRs space are both-byte and bit-addressable. The bitaddressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh. Table 3.
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uPSD3212A, uPSD3212C, uPSD3212CV (3) Register addressing. The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of four banks is selected at execution time by the two bank select bits in the PSW.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 4. Arithmetic Instructions Addressing Modes Mnemonic Operation Dir. Ind. Reg.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 5. Logical Instructions Addressing Modes Mnemonic Operation Dir. Ind. Reg. Imm X X X X X X X X X ANL A, A = A .AND. X ANL ,A A = .AND. A X ANL ,#data A = .AND. #data X ORL A, A = A .OR. X ORL ,A A = .OR. A X ORL ,#data A = .OR. #data X XRL A, A = A .XOR. X XRL ,A A = .XOR. A X XRL ,#data A = .XOR.
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uPSD3212A, uPSD3212C, uPSD3212CV Data Transfers Internal RAM. Table 6 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. The MOV , instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator. Remember, the Upper 128 bytes of data RAM can be accessed only by indirect addressing, and SFR space only by direct addressing.
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uPSD3212A, uPSD3212C, uPSD3212CV First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed which leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location 2DH. The CJNE instruction (Compare and Jump if Not equal) is a loop control that will be described later. The loop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH, and 2BH.
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uPSD3212A, uPSD3212C, uPSD3212CV External RAM. Table 10 shows a list of the Data Transfer instructions that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a one-byte address, @Ri, where Ri can be either R0 or R1 of the selected register bank, or a two-byte address, @DTPR. Note: In all external Data RAM accesses, the Accumulator is always either the destination or source of the data. Lookup Tables.
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uPSD3212A, uPSD3212C, uPSD3212CV Boolean Instructions The uPSD321x Devices contain a complete Boolean (single-bit) processor. One page of the internal RAM contains 128 addressable bits, and the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one can be treated as a separate singlebit port. The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, OR and AND instructions.
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uPSD3212A, uPSD3212C, uPSD3212CV Jump Instructions Table 13 shows the list of unconditional jump instructions. The table lists a single “JMP add” instruction, but in fact there are three SJMP, LJMP, and AJMP, which differ in the format of the destination address. JMP is a generic mnemonic which can be used if the programmer does not care which way the jump is en-coded. The SJMP instruction encodes the destination address as a relative offset, as described above.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 14 shows the list of conditional jumps available to the uPSD321x Devices user. All of these jumps specify the destination address by the relative offset method, and so are limited to a jump distance of -128 to +127 bytes from the instruction following the conditional jump instruction. Important to note, however, the user specifies to the assembler the actual destination address the same way as the other jumps: as a label or a 16-bit constant.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 14. State Sequence in uPSD321x Devices Osc. (XTAL2) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 Read next opcode and discard Read opcode S1 S2 S3 S4 S5 Read next opcode S6 a. 1-Byte, 1-Cycle Instruction, e.g. INC A S1 S2 Read next opcode Read 2nd Byte Read opcode S3 S4 S5 S6 b. 2-Byte, 1-Cycle Instruction, e.g.
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uPSD3212A, uPSD3212C, uPSD3212CV uPSD3200 HARDWARE DESCRIPTION The uPSD321x Devices has a modular architecture with two main functional modules: the MCU Module and the PSD Module. The MCU Module consists of a standard 8032 core, peripherals and other system supporting functions. The PSD Module provides configurable Program and Data memories to the 8032 CPU core. In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation.
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uPSD3212A, uPSD3212C, uPSD3212CV MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and Peripherals, including: ■ Special Function Registers ■ Timers/Counter ■ Interrupts ■ PWM ■ Supervisory Function (LVD and Watchdog) ■ USART ■ Power Saving Modes ■ I2C Bus ■ On-chip Oscillator ■ ADC ■ I/O Ports Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 15.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 16.
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uPSD3212A, uPSD3212C, uPSD3212CV SFR Reg Name Addr Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value A4 PWM2 00 PWM2 Output Duty Cycle A5 PWM3 00 PWM3 Output Duty Cycle A6 WDRST 00 Watch Dog Reset A7 IEA 00 Interrupt Enable (2nd) A8 IE 00 Interrupt Enable EI2C ES2 EA - ET2 ES ET1 EX1 ET0 EX0 A9 AA PWM4P 00 PWM 4 Period AB PWM4W 00 PWM 4 Pulse Width AE WDKEY 00 Watch Dog Key Register B0 P3 FF Port 3 B1 PSCL0L 00 Prescaler 0 Low (8-bit) B2 PSCL0
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uPSD3212A, uPSD3212C, uPSD3212CV SFR Reg Name Addr Bit Register Name 7 6 5 4 3 2 1 0 D2 S2SETUP Reset Comments Value 00 I2C (S2) Setup D4 D5 D6 D7 D8 D9 DA DB DC S2CON CR2 EN1 STA STO ADDR AA CR1 CR0 00 I2C Bus Control Reg DD S2STA GC Stop Intr TX-Md Bbusy Blost ACK_R SLV 00 I2C Bus Status DE S2DAT 00 Data Hold Register DF S2ADR 00 I2C address E0 ACC 00 Accumulator E1 USCL E6 UDT1 E7 00 8-bit Prescaler for USB logic www.BDTIC.com/ST UDT1.7 UDT1.6 UDT1.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 17. PSD Module Register Address Offset CSIOP Addr Offset Register Name 00 Data In (Port A) Reads Port pins as input 02 Control (Port A) Configure pin between I/O or Address Out Mode. Bit = 0 selects I/ O 00 04 Data Out (Port A) Latched data for output to Port pins, I/O Output Mode 00 06 Direction (Port A) Configures Port pin as input or output. Bit = 0 selects input 00 08 Drive (Port A) Configures Port pin between CMOS, Open Drain or Slew rate.
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uPSD3212A, uPSD3212C, uPSD3212CV CSIOP Addr Offset Register Name 21 Output Macrocells BC 22 Mask Macrocells AB 23 Mask Macrocells BC C0 Primary Flash Protection C2 Bit Register Name 7 Secondary Flash Security Protection _Bit B0 PMMR0 * B4 PMMR2 * E0 Page E2 VM Periphmode 6 * * 5 * * 3 * PLD array Cntl2 FL_ data 2 1 0 Reset Value Comments Sec3_ Sec2_ Sec1_ Prot Prot Prot Sec0_ Prot Bit = 1 sector is protected * Sec1_ Prot Sec0_ Prot Security Bit = 1 device is secu
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uPSD3212A, uPSD3212C, uPSD3212CV INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows (see Figure 16., page 35). ■ INT0 External Interrupt ■ 2nd USART Interrupt ■ Timer 0 Interrupt ■ I2C Interrupt ■ INT1 External Interrupt (or ADC Interrupt) ■ Timer 1 Interrupt ■ USB Interrupt ■ USART Interrupt ■ Timer 2 Interrupt External Int0 – The INT0 can be either level-active or transition-active depending on Bit IT0 in register TCON.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 16. Interrupt System Interrupt Sources IP / IPA Priority IE / High INT0 Low USART Timer 0 I2C Interrupt Polling INT1 Timer 1 USB 2nd USART Timer 2 www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV USART Interrupt – The USART Interrupt is generated by RI (Receive Interrupt) OR TI (Transmit Interrupt). – When the USART Interrupt is generated, the corresponding request flag must be cleared by the software. The interrupt service routine will have to check the various USART registers to determine the source and clear the corresponding flag.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 20. Description of the IE Bits. Bit Symbol Function 7 EA Disable all interrupts: 0: no interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit 6 — Reserved 5 ET2 Enable Timer 2 Interrupt 4 ES Enable USART Interrupt 3 ET1 Enable Timer 1 Interrupt 2 EX1 Enable External Interrupt (Int1) 1 ET0 Enable Timer 0 Interrupt 0 EX0 Enable External Interrupt (Int0) Table 21.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 23. Description of the IPA Bits Bit Symbol Function 7 — Not used 6 — Not used 5 — Not used 4 PS2 3 — Not used 2 — Not used 1 PI2C I²C Interrupt priority level 0 PUSB USB Interrupt priority level 2nd USART Interrupt priority level How Interrupts are Handled The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during following machine cycle.
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uPSD3212A, uPSD3212C, uPSD3212CV POWER-SAVING MODE Two software selectable modes of reduced power consumption are implemented (see Table 25). Idle Mode The following Functions are Switched Off. – CPU (Halted) The following Function Remain Active During Idle Mode. – External Interrupts – Timer 0, Timer 1, Timer 2 – PWM Units – USART – 8-bit ADC – I2C Interface – USB Interface Note: Interrupt or RESET terminates the Idle Mode.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 27. Description of the PCON Bits Bit Symbol Function 7 SMOD Double Baud Data Rate Bit UART 6 SMOD1 Double Baud Data Rate Bit 2nd UART 5 LVREN LVR Disable Bit (active High) 4 ADSFINT 3 RCLK1 (1) 2 TCLK1(1) 1 PD Activate Power-down Mode (High enable) 0 IDL Activate Idle Mode (High enable) Enable ADC Interrupt Received Clock Flag (UART 2) Transmit Clock Flag (UART 2) Note: 1.
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uPSD3212A, uPSD3212C, uPSD3212CV The following SFR registers (Tables 29, 30, and 31) are used to control the mapping of alternate functions onto the I/O port bits. Port 1 alternate functions are controlled using the P1SFS register, except for Timer 2 and the 2nd UART which are enabled by their configuration registers. P1.0 to P1.3 are default to GPIO after reset. Port 3 pins 6 and 7 have been modified from the standard 8032.
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uPSD3212A, uPSD3212C, uPSD3212CV PORT Type and Description Figure 17. PORT Type and Description (Part 1) Symbol In / Out RESET I Circuit Description • Schmitt input with internal pull-up CMOS compatible interface NFC : 400ns NFC WR, RD,ALE, PSEN O XTAL1, XTAL2 I Output only On-chip oscillator On-chip feedback resistor Stop in the power down mode External clock input available CMOS compatible interface www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 18. PORT Type and Description (Part 2) In/ Out Symbol PORT1 <3:0>, PORT3, PORT4<7:3,1:0> Circuit Function I/O Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface I/O Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface Analog input option PORT2 PORT1 < 7:4 > an_enb Bidirectional I/O port with internal I/O PORT4.2 pull-ups Schmitt input. TTL compatible interface www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV OSCILLATOR The oscillator circuit of the uPSD321x Devices is a single stage inverting amplifier in a Pierce oscillator configuration (see Figure 19). The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback ele- ment to complete the oscillator circuit. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output.
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uPSD3212A, uPSD3212C, uPSD3212CV SUPERVISORY There are four ways to invoke a reset and initialize the uPSD321x Devices. ■ Via the external RESET pin ■ Via the internal LVR Block. ■ Via Watch Dog timer ■ Via USB bus reset signalling The RESET mechanism is illustrated in Figure 20. Each RESET source will cause an internal reset signal active. The CPU responds by executing an internal reset and puts the internal registers in a defined state.
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uPSD3212A, uPSD3212C, uPSD3212CV WATCHDOG TIMER The hardware Watchdog Timer (WDT) resets the uPSD321x Devices when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer.
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uPSD3212A, uPSD3212C, uPSD3212CV Watchdog reset pulse width depends on the clock frequency. The reset period is TfOSC x 12 x 222. The RESET pulse width is TfOSC x 12 x 215. Figure 21. RESET Pulse Width Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz) Reset period (1.258 second at 40Mhz) (about 6.291 seconds at 8Mhz) AI06823 Table 34. Watchdog Timer Clear Register (WDRST: 0A6H) 7 6 5 4 3 2 1 0 Reserved WDRST6 WDRST5 WDRST4 WDRST3 WDRST2 WDRST1 WDRST0 Table 35.
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uPSD3212A, uPSD3212C, uPSD3212CV TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) The uPSD321x Devices has three 16-bit Timer/ Counter registers: Timer 0, Timer 1 and Timer 2. All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. In the “Timer” function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 39. Description of the TMOD Bits Bit Symbol Timer 7 Gate Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set 6 C/T Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T1 input pin) 5 M1 4 M0 3 Gate Gating control when set.
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uPSD3212A, uPSD3212C, uPSD3212CV Mode 0. Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 22 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt Flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or /INT1 = 1.
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uPSD3212A, uPSD3212C, uPSD3212CV Mode 2. Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 23. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Timer 2 Like Timer 0 and 1, Timer 2 can operate as either an event timer or as an event counter.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 41. Timer/Counter 2 Operating Modes T2CON Mode 16-bit Autoreload Input Clock RxCLK or TxCLK CP/ RL2 TR2 T2MOD DECN T2CON EXEN P1.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 24. Timer 2 in Capture Mode fOSC ÷ 12 C/T2 = 0 C/T2 = 1 T2 pin TL2 (8 bits) TH2 (8 bits) TF2 Control TR2 Timer 2 Interrupt Capture RCAP2L RCAP2H Transition Detector T2EX pin EXP2 Control EXEN2 AI06625 Figure 25. Timer 2 in Auto-Reload Mode fOSC www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 26. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1“ Interrupt.
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uPSD3212A, uPSD3212C, uPSD3212CV STANDARD SERIAL INTERFACE (UART) The uPSD321x Devices provides two standard 8032 UART serial ports. The first port is connected to pin P3.0 (RX) and P3.1 (TX). The second port is connected to pin P1.2 (RX) and P1.3(TX). The operation of the two serial ports are the same and are controlled by the SCON and SCON2 registers. The serial port is full duplex, meaning it can transmit and receive simultaneously.
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uPSD3212A, uPSD3212C, uPSD3212CV Serial Port Control Register The serial port control and status register is the Special Function Register SCON (SCON2 for the second port), shown in Figure 27. This register (see Tables 43 and 44) contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the Serial Port Interrupt Bits (TI and RI). Figure 27. Serial Port Mode 0, Block Diagram Internal Bus Write to SBUF D S Q CL RxD P3.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 44. Description of the SCON Bits Bit Symbol 7 SM0 6 SM1 Function (SM1,SM0)=(0,0): Shift Register. Baud rate = fOSC/12 (SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable (SM1,SM0)=(0,1): 8-bit UART. Baud rate = fOSC/64 or fOSC/32 (SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable 5 SM2 Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.
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uPSD3212A, uPSD3212C, uPSD3212CV Baud Rates. The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of Bit SMOD = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2 SMOD / 64) x fOSC In the uPSD321x Devices, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to Generate Baud Rates.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 45. Timer 1-Generated Commonly Used Baud Rates Baud Rate fOSC SMOD Timer 1 C/T Mode Reload Value Mode 0 Max: 1MHz 12MHz X X X X Mode 2 Max: 375K 12MHz 1 X X X Modes 1, 3: 62.5K 12MHz 1 0 2 FFh 19.2K 11.059MHz 1 0 2 FDh 9.6K 11.059MHz 0 0 2 FDh 4.8K 11.059MHz 0 0 2 FAh 2.4K 11.059MHz 0 0 2 F4h 1.2K 11.059MHz 0 0 2 E8h 137.5 11.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 28. Serial Port Mode 0, Waveforms Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) T S6P2 D0 D1 S3P1 D2 D3 D4 D5 D6 Transmit D7 S6P1 Write to SCON RI Receive Shift RxD (Data In) TxD (Shift Clock) Clear RI Receive D0 D1 D2 D3 D4 D5 D6 D7 AI06825 More About Mode 1. Ten bits are transmitted (through TxD), or received (through RxD): a start Bit (0), 8 data bits (LSB first). and a Stop Bit (1).
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 29. Serial Port Mode 1, Block Diagram Timer1 Overflow Timer2 Overflow Internal Bus TB8 Write to SBUF D S Q CL ÷2 0 TxD SBUF 1 Zero Detector SMOD 0 1 Shift Start TCLK Tx Control ÷16 0 Tx Clock Data Send TI Serial Port Interrupt 1 RCLK ÷16 Sample Rx Clock 1-to-0 Transition Detector Load SBUF RI Shift Rx Control 1FFh Start Rx Detector Input Shift Register www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV More About Modes 2 and 3. Eleven bits are transmitted (through TxD), or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of '0' or '1.' On receive, the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figure 31.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 31. Serial Port Mode 2, Block Diagram Phase2 Clock 1/2*fOSC Internal Bus TB8 Write to SBUF D S Q CL ÷2 0 TxD SBUF 1 Zero Detector SMOD Shift Start Tx Control ÷16 Tx Clock Data Send TI Serial Port Interrupt ÷16 Sample Load SBUF RI Rx Clock 1-to-0 Transition Detector Shift Rx Control 1FFh Start Rx Detector Input Shift Register www.BDTIC.com/ST Load SBUF RxD Shift SBUF Read SBUF Internal Bus AI06844 Figure 32.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 33. Serial Port Mode 3, Block Diagram Timer1 Overflow Timer2 Overflow Internal Bus TB8 Write to SBUF D S Q CL ÷2 0 TxD SBUF 1 Zero Detector SMOD 0 1 Shift Start TCLK Tx Control ÷16 0 Tx Clock Data Send TI Serial Port Interrupt 1 RCLK ÷16 Sample Load SBUF RI Rx Clock 1-to-0 Transition Detector Shift Rx Control 1FFh Start Rx Detector Input Shift Register www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV ANALOG-TO-DIGITAL CONVERTOR (ADC) matically when A/D conversion is completed, cleared when A/D conversion is in process. The ASCL should be loaded with a value that results in a clock rate of approximately 6MHz for the ADC using the following formula (see Table 48.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 46. ADC SFR Memory Map SFR Addr Reg Name 95 ASCL 96 ADAT 97 ACON Bit Register Name 7 ADAT7 6 ADAT6 5 4 ADAT5 3 ADAT4 ADEN 2 1 Reset Comments Value 0 00 8-bit Prescaler for ADC clock ADAT3 ADAT2 ADAT1 ADAT0 00 ADC Data Register ADS1 ADS0 ADST ADSF 00 ADC Control Register Table 47.
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uPSD3212A, uPSD3212C, uPSD3212CV PULSE WIDTH MODULATION (PWM) The PWM block has the following features: ■ Four-channel, 8-bit PWM unit with 16-bit prescaler ■ One-channel, 8-bit unit with programmable frequency and pulse width ■ PWM Output with programmable polarity 4-channel PWM Unit (PWM 0-3) The 8-bit counter of a PWM counts module 256 (i.e., from 0 to 255, inclusive). The value held in the 8-bit counter is compared to the contents of the Special Function Register (PWM 0-3) of the corresponding PWM.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 36. Four-Channel 8-bit PWM Block Diagram DATA BUS x4 8 8 CPU rd/wr 8-bit PWM0-PWM3 Data Registers 8 x4 8 load 8-bit PWM0-PWM3 Comparators Registers 8 x4 16-bit Prescaler Register (B2h,B1h) CPU rd/wr 8-bit PWM0-PWM3 Comparators Port4.3 Port4.4 Port4.5 Port4.6 4 PWMCON bit7 (PWML) 16 8 fOSC/2 www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 49.
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uPSD3212A, uPSD3212C, uPSD3212CV Programmable Period 8-bit PWM The PWM 4 channel can be programmed to provide a PWM output with variable pulse width and period. The PWM 4 has a 16-bit Prescaler, an 8bit Counter, a Pulse Width Register, and a Period Register. The Pulse Width Register defines the PWM pulse width time, while the Period Register defines the period of the PWM. The input clock to the Prescaler is fOSC/2. The PWM 4 channel is assigned to Port 4.7. Figure 37.
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uPSD3212A, uPSD3212C, uPSD3212CV PWM 4 Channel Operation The 16-bit Prescaler1 divides the input clock (fOSC/2) to the desired frequency, the resulting clock runs the 8-bit Counter of the PWM 4 channel. The input clock frequency to the PWM 4 Counter is: f PWM4 = (fOSC/2)/(Prescaler1 data value +1) When the Prescaler1 Register (B4h, B3h) is set to data value '0,' the maximum input clock frequency to the PWM 4 Counter is fOSC/2 and can be as high as 20MHz. The PWM 4 Counter is a free-running, 8-bit counter.
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uPSD3212A, uPSD3212C, uPSD3212CV I2C INTERFACE The serial port supports the twin line I2C-bus, consisting of a data line (SDA1), and a clock line (SCL1) as shown in Figure 39. Depending on the configuration, the SDA1 and SCL1 lines may require pull-up resistors. These lines also function as I/O port lines if the I2C bus is not enabled. The system is unique because data transport, clock generation, address recognition, and bus control arbitration are all controlled by hardware.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 51. Description of the S2CON Bits Bit Symbol Function 7 CR2 This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is in the Master Mode. 6 ENII Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high impedance state. 5 STA START Flag. When this bit is set, the SIO H/W checks the status of the I2C-bus and generates a START condition if the bus free.
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uPSD3212A, uPSD3212C, uPSD3212CV Serial Status Register (S2STA) S2STA is a “Read-only” register. The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I2C bus. The status codes for all possible modes of the I2C bus interface are given Table 54. This flag is set, and an interrupt is generated, after any of the following events occur: 1. Own slave address has been received during AA = 1: ack_int 2.
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uPSD3212A, uPSD3212C, uPSD3212CV Address Register (S2ADR) This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/transmitter. The Start/Stop Hold Time Detection and System Clock registers (Tables 57 and 58) are included in the I2C unit to specify the start/stop detection time to work with the large range of MCU frequency values supported. For example, with a system clock of 40MHz. Table 56.
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uPSD3212A, uPSD3212C, uPSD3212CV USB HARDWARE The characteristics of USB hardware are as follows: ■ Complies with the Universal Serial Bus specification Rev. 1.1 ■ Integrated SIE (Serial Interface Engine), FIFO memory and transceiver ■ Low speed (1.5Mbit/s) device capability ■ Supports control endpoint0 and interrupt endpoint1 and 2 ■ USB clock input must be 6MHz (requires MCU clock frequency to be 12, 24, or 36MHz). The analog front-end is an on-chip generic USB transceiver.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 62. USB Interrupt Enable Register (UIEN: 0E9h) 7 6 5 4 3 2 1 0 SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI Table 63. Description of the UIEN Bits Bit Symbol R/W Function 7 SUSPNDI R/W Enable SUSPND Interrupt 6 RSTE R/W Enable USB Reset; also resets the CPU and PSD Modules when bit is set to '1.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 64. USB Interrupt Status Register (UISTA: 0E8h) 7 6 5 4 3 2 1 0 SUSPND — RSTF TXD0F RXD0F TXD1F EOPF RESUMF Table 65. Description of the UISTA Bits Bit Symbol R/W Function USB Suspend Mode Flag. To save power, this bit should be set if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend Mode.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 66. USB Endpoint0 Transmit Control Register (UCON0: 0EAh) 7 6 5 4 3 2 1 0 TSEQ0 STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 Table 67. Description of the UCON0 Bits Bit 7 6 5 4 3 to 0 Symbol R/W Function R/W Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) 7 6 5 4 3 2 1 0 TSEQ1 EP12SEL TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 Table 69. Description of the UCON1 Bits Bit 7 6 5 Symbol TSEQ1 EP12SEL TX1E R/W Function R/W Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 70. USB Control Register (UCON2: 0ECh) 7 6 5 4 3 2 1 0 — — — SOUT EP2E EP1E STALL2 STALL1 Table 71. Description of the UCON2 Bits Bit Symbol R/W Function 7 to 5 — — 4 SOUT R/W Status out is used to automatically respond to the OUT of a control READ transfer 3 EP2E R/W Endpoint2 enable. RESET clears this bit 2 EP1E R/W Endpoint1 enable. RESET clears this bit 1 STALL2 R/W Endpoint2 Force Stall Bit.
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uPSD3212A, uPSD3212C, uPSD3212CV The USCL 8-bit Prescaler Register for USB is at E1h. The USCL should be loaded with a value that results in a clock rate of 6MHz for the USB using the following formula: USB clock input = (fOSC / 2) / (Prescaler register value +1) Where fOSC is the MCU clock input frequency. Note: USB works ONLY with the MCU Clock frequencies of 12, 24, or 36MHz. The Prescaler values for these frequencies are 0, 1, and 2. Table 77.
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uPSD3212A, uPSD3212C, uPSD3212CV Transceiver USB Physical Layer Characteristics. The following section describes the uPSD321x Devices compliance to the Chapter 7 Electrical section of the USB Specification, Revision 1.1. The section contains all signaling, and physical layer specifications necessary to describe a low speed USB function. Low Speed Driver Characteristics. The uPSD321x Devices use a differential output driver to drive the Low Speed USB data signal onto the USB cable.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 78. Transceiver DC Characteristics Symb Parameter Test Conditions(1) Min Max Unit VOH Static Output High 15kΩ ± 5% to GND(2,3) 2.8 3.6 V VOL Static Output Low Notes 2, 3 — 0.3 V VDI Differential Input Sensitivity |(D+) - (D-)|, Figure 43., page 86 0.2 — V VCM Differential Input Common Mode Figure 43., page 86 0.8 2.5 V VSE Single Ended Receiver Threshold — 0.8 2.
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uPSD3212A, uPSD3212C, uPSD3212CV Receiver Characteristics The uPSD321x Devices has a differential input receiver which is able to accept the USB data signal. The receiver features an input sensitivity of at least 200mV when both differential data inputs are in the range of at least 0.8V to 2.5V with respect to its local ground reference. This is the common mode range, as shown in Figure 41. The receiver tolerates static input voltages between -0.5V to 3.
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uPSD3212A, uPSD3212C, uPSD3212CV External USB Pull-Up Resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5kΩ pull-up resistor to a 3.3V supply. An approved alternative method is a 7.5kΩ pull-up to the USB VCC supply. This alterna- tive is defined for low-speed devices with an integrated cable. The chip is specified for the 7.5kΩ pull-up. This eliminates the need for an external 3.3V regulator, or for a pin dedicated to providing a 3.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 44. Differential to EOP Transition Skew and EOP Width TPERIOD Crossover Point Extended Crossover Point Differential Data Lines Diff. Data to SE0 Skew N*TPERIOD+TDEOP Source EOP Width: TEOPT Receiver EOP Width TEOPR1, TEOPR2 AI06633 Figure 45. Differential Data Jitter TPERIOD Differential Data Lines Crossover Points www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV PSD MODULE The PSD Module provides configurable Program and Data memories to the 8032 CPU core (MCU). In addition, it has its own set of I/ O ports and a PLD with 16 macrocells for general logic implementation. ■ Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU Module.
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D0 – D7 WR_, RD_, PSEN_, ALE, RESET_, A0-A15 8032 Bus CLKIN (PD1) GLOBAL CONFIG.
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uPSD3212A, uPSD3212C, uPSD3212CV In-System Programming (ISP) Using the JTAG signals on Port C, the entire PSD MODULE device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory.
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uPSD3212A, uPSD3212C, uPSD3212CV DEVELOPMENT SYSTEM The uPSD3200 is supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD MODULE design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD MODULE pin functions and memory map information. The general design flow is shown in Figure 47.
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uPSD3212A, uPSD3212C, uPSD3212CV PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET Table 81 shows the offset addresses to the PSD MODULE registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD MODULE registers. Table 81 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Table 81.
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uPSD3212A, uPSD3212C, uPSD3212CV PSD MODULE DETAILED OPERATION As shown in Figure 15., page 27, the PSD MODULE consists of five major types of functional blocks: ■ Memory Block ■ PLD Blocks ■ I/O Ports ■ Power Management Unit (PMU) ■ JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.
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uPSD3212A, uPSD3212C, uPSD3212CV Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD MODULE and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 82.
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uPSD3212A, uPSD3212C, uPSD3212CV Power-down Instruction and Power-up Mode Power-up Mode. The PSD MODULE internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS3 and CSBOOT0CSBOOT1) must be held Low, and WRITE Strobe (WR, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO.
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uPSD3212A, uPSD3212C, uPSD3212CV Toggle Flag (DQ6). The Flash memory offers another way for determining when the Program cycle is completed. During the internal WRITE operation and when either the FS0-FS3 or CSBOOT0CSBOOT1 is true, the Toggle Flag Bit (DQ6) toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data READ on the Data Bus D0-D7 is the addressed memory byte.
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uPSD3212A, uPSD3212C, uPSD3212CV Programming Flash Memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all '1s' (FFh), and is programmed by setting selected bits to '0.' The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-bybyte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 82).
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uPSD3212A, uPSD3212C, uPSD3212CV Data Toggle. Checking the Toggle Flag Bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 49 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status.
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uPSD3212A, uPSD3212C, uPSD3212CV Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 82. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Flash memory status.
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uPSD3212A, uPSD3212C, uPSD3212CV Specific Features Flash Memory Sector Protect. Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program.
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uPSD3212A, uPSD3212C, uPSD3212CV SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Standby (VSTBY, PC2). If you have an external battery connected to the uPSD3200, the contents of the SRAM are retained in the event of a power loss.
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uPSD3212A, uPSD3212C, uPSD3212CV Memory Select Configuration in Program and Data Spaces. The MCU Core has separate address spaces for Program memory and Data memory. Any of the memories within the PSD MODULE can reside in either space or both spaces. This is controlled through manipulation of the VM Register that resides in the CSIOP space. The VM Register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly.
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uPSD3212A, uPSD3212C, uPSD3212CV Separate Space Mode. Program space is separated from Data space. For example, Program Select Enable (PSEN) is used to access the program code from the primary Flash memory, while READ Strobe (RD) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM Register to be set to 0Ch (see Figure 51). Combined Space Modes.
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uPSD3212A, uPSD3212C, uPSD3212CV Page Register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0FS3, CSBOOT0-CSBOOT1), and SRAM Select (RS0) equations.
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uPSD3212A, uPSD3212C, uPSD3212CV PLDS The PLDs bring programmable logic functionality to the uPSD. After specifying the logic for the PLDs in PSDsoft Express, the logic is programmed into the device and available upon Power-up. Table 87.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 54. PLD Diagram 8 PAGE REGISTER DECODE PLD 73 4 PRIMARY FLASH MEMORY SELECTS 2 SECONDARY NON-VOLATILE MEMORY SELECTS 1 SRAM SELECT 1 CSIOP SELECT PLD INPUT BUS 2 16 PERIPHERAL SELECTS DIRECT MACROCELL ACCESS FROM MCU DATA BUS OUTPUT MACROCELL FEEDBACK CPLD 16 OUTPUT MACROCELL PT ALLOC. 73 20 INPUT MACROCELL (PORT A,B,C) MACROCELL ALLOC.
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uPSD3212A, uPSD3212C, uPSD3212CV Decode PLD (DPLD) The DPLD, shown in Figure 55, is used for decoding the address for PSD MODULE and external components.
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uPSD3212A, uPSD3212C, uPSD3212CV Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port D. Although External Chip Select (ECS1-ECS2) can be produced by any Output Macrocell (OMC), these External Chip Select (ECS1-ECS2) on Port D do not consume any Output Macrocells (OMC).
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uPSD3212A, uPSD3212C, uPSD3212CV Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a McellBC output on Port B or C. Table 88 shows the macrocells and port assignment.
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uPSD3212A, uPSD3212C, uPSD3212CV Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to another.
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uPSD3212A, uPSD3212C, uPSD3212CV The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked from writing to the associated Output Macrocells (OMC).
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uPSD3212A, uPSD3212C, uPSD3212CV I/O PORTS (PSD MODULE) There are four programmable I/O ports: Ports A, B, C, and D in the PSD MODULE. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. Port A is not available in the 52-pin package.
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uPSD3212A, uPSD3212C, uPSD3212CV The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 60. Peripheral I/O Mode RD PSEL0 PSEL PSEL1 D0 - D7 VM REGISTER BIT 7 PA0 - PA7 DATA BUS WR AI02886 Table 89. Port Operating Modes Port A(2) Port Mode Port B Port C Port D MCU I/O Yes Yes Yes Yes PLD I/O McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs Yes No No Yes Yes Yes No Yes No Yes(3) No Yes No No Yes Yes Address Out Yes (A7 – 0) Yes (A7 – 0) No No Yes No No No No No Yes(1) No Peripheral I/O JTAG ISP www.
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uPSD3212A, uPSD3212C, uPSD3212CV Port Configuration Registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 81., page 92. The addresses in Table 81 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin.
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uPSD3212A, uPSD3212C, uPSD3212CV Port Data Registers The Port Data Registers, shown in Table 97, are used by the MCU to write data to or read data from the ports. Table 97 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. Data In. Port pins are connected directly to the Data In buffer. In MCU I/O Input Mode, the pin input is read through the Data In buffer. Data Out Register.
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uPSD3212A, uPSD3212C, uPSD3212CV Ports A and B – Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 61. The two ports can be configured to perform one or more of the following functions: ■ MCU I/O Mode ■ CPLD Output – Macrocells McellAB7McellAB0 can be connected to Port A or Port B. McellBC7-McellBC0 can be connected to Port B or Port C. ■ ■ ■ ■ CPLD Input – Via the Input Macrocells (IMC).
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uPSD3212A, uPSD3212C, uPSD3212CV Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 62): ■ MCU I/O Mode ■ CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. ■ CPLD Input – via the Input Macrocells (IMC) ■ In-System Programming (ISP) – JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins for device programming.
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uPSD3212A, uPSD3212C, uPSD3212CV Port D – Functionality and Structure Port D has two I/O pins (only one pin, PD1, in the 52-pin package). See Figure 63 and Figure 64., page 121. This port does not support Address Out Mode, and therefore no Control Register is required. Of the eight bits in the Port D registers, only Bits 2 and 1 are used to configure pins PD2 and PD1.
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uPSD3212A, uPSD3212C, uPSD3212CV External Chip Select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 64.) Figure 64. Port D External Chip Select Signals ENABLE (.
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uPSD3212A, uPSD3212C, uPSD3212CV POWER MANAGEMENT All PSD MODULE offers configurable power saving options. These options may be used individually or in combinations, as follows: – The primary and secondary Flash memory, and SRAM blocks are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current).
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uPSD3212A, uPSD3212C, uPSD3212CV The PSD MODULE has a Turbo Bit in PMMR0. This bit can be set to turn the Turbo Mode off (the default is with Turbo Mode turned on). While Turbo Mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is on. When the Turbo Mode is on, there is a significant DC current component and the AC component is higher.
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uPSD3212A, uPSD3212C, uPSD3212CV PLD Power Management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0 (see Table 99). By setting the bit to '1,' the Turbo Mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns (for a 5V device) after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15MHz.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 100. Power Management Mode Registers PMMR2 Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. PLD Array WR 0 = on WR input to the PLD AND Array is connected. Bit 2 PLD Array RD 0 = on RD input to the PLD AND Array is connected. Bit 3 1 = off WR input to PLD AND Array is disconnected, saving power. 1 = off RD input to PLD AND Array is disconnected, saving power.
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uPSD3212A, uPSD3212C, uPSD3212CV RESET TIMING AND DEVICE STATUS AT RESET Upon Power-up, the PSD MODULE requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. After the rising edge of Reset (RESET), the PSD MODULE remains in the Reset Mode for an additional period, tOPR, before the first memory access is allowed.
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uPSD3212A, uPSD3212C, uPSD3212CV PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface pins (TMS, TCK, TDI, TDO) are dedicated pins on Port C (see Table 103). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD MODULE Configuration Register Bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO.
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uPSD3212A, uPSD3212C, uPSD3212CV AC/DC PARAMETERS The following are issues concerning the parameters presented: – In the DC specification the supply current is given for different modes of operation. – The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures 68 and 69 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. – In the PLD timing parameters, add the required delay when Turbo Bit is '0.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.
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uPSD3212A, uPSD3212C, uPSD3212CV MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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uPSD3212A, uPSD3212C, uPSD3212CV EMC CHARACTERISTICS Susceptibility test are performed on a sample basis during product characterization. Functional EMS (Electromagnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD. Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs.
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uPSD3212A, uPSD3212C, uPSD3212CV LU. 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output, and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC Latch-up Standard (see Table 108). For more details, refer to the Application Note, AN1181. DLU.
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uPSD3212A, uPSD3212C, uPSD3212CV DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 109.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 70. Switching Waveforms – Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM HI TO LO WILL BE CHANGING FROM HI TO LO MAY CHANGE FROM LO TO HI WILL BE CHANGING LO TO HI DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 113. Major Parameters Parameters/Conditions/ Comments 5V Test Conditions 5.0V Value 3.3V Test Conditions 3.3V Value Operating Voltage – 4.5 to 5.5 – 3.0 to 3.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 114. DC Characteristics (5V Devices) Symbol Parameter Test Condition (in addition to those in Table 109., page 133) Min. VIH Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 4.5V < VCC < 5.5V VIH1 Input High Voltage (Ports A, B, C, D, 4[Bit 2]) VIL VIL1 VOL Max. Unit 0.7VCC VCC + 0.5 V 4.5V < VCC < 5.5V 2.0 VCC + 0.5 V Input Low Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 4.5V < VCC < 5.5V VSS – 0.5 0.
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uPSD3212A, uPSD3212C, uPSD3212CV Symbol Parameter Test Condition (in addition to those in Table 109., page 133) ISTBY SRAM (PSD) Standby Current (VSTBY input) VCC = 0V IIDLE SRAM (PSD) Idle Current (VSTBY input) VCC > VSTBY IRST Reset Pin Pull-up Current (RESET) IFR XTAL Feedback Resistor Current (XTAL1) ILI Input Leakage Current ILO IPD (1) Typ. Max. Unit 0.5 1 µA –0.1 0.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 115. DC Characteristics (3V Devices) Symbol Parameter Test Condition (in addition to those in Table 110., page 133) Min. VIH Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], A, B, C, D, XTAL1, RESET) 3.0V < VCC < 3.6V VIH1 Input High Voltage (Port 4[Bit 2]) VIL VIL1 VOL VOL1 VOL2 VOH VOH1 VOH2 Max. Unit 0.7VCC VCC + 0.5 V 3.0V < VCC < 3.6V 2.0 VCC + 0.5 V Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 3.
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uPSD3212A, uPSD3212C, uPSD3212CV Symbol Parameter Test Condition (in addition to those in Table 110., page 133) ITL Logic 1-to-0 Transition Current (Ports 1,2,3,4) VIN = 3.5V (2.5V for Port 4[pin 2]) ISTBY SRAM (PSD) Standby Current (VSTBY input) VCC = 0V IIDLE SRAM (PSD) Idle Current (VSTBY input) VCC > VSTBY IRST Reset Pin Pull-up Current (RESET) IFR XTAL Feedback Resistor Current (XTAL1) ILI Input Leakage Current ILO IPD (1) Max. Unit –250 µA 1 µA –0.1 0.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 71. External Program Memory READ Cycle tLLPL tLHLL ALE tAVLL tPLPH tLLIV tPLIV PSEN tPXAV tLLAX tPXIZ tAZPL PORT 0 INSTR IN A0-A7 tAVIV A0-A7 tPXIX A8-A11 PORT 2 A8-A11 AI06848 Table 116. External Program Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter(1) 40MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 117.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 72. External Data Memory READ Cycle ALE tLHLL tWHLH PSEN tLLDV tLLWL tRLRH RD tLLAX2 tRLAZ A0-A7 from RI or DPL PORT 0 tRHDZ tRLDV tAVLL tRHDX DATA IN A0-A7 from PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07088 Table 118. External Clock Drive (with the 5V MCU Module) Parameter(1) Symbol 40MHz Oscillator Variable Oscillator 1/tCLCL = 24 to 40MHz www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 73. External Data Memory WRITE Cycle ALE tLHLL tWHLH PSEN tLLWL tWLWH WR tLLAX A0-A7 from RI or DPL PORT 0 tWHQX tQVWX tAVLL tQVWH DATA OUT A0-A7 from PCL INSTR IN tAVWL PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07089 Table 120.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 121.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 74. Input to Output Disable / Enable INPUT tER tEA INPUT TO OUTPUT ENABLE/DISABLE AI02863 Table 123.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 75. Synchronous Clock Mode Timing – PLD tCH tCL CLKIN tS tH INPUT tCO REGISTERED OUTPUT AI02860 Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit 1/(tS+tCO) 40.0 MHz 1/(tS+tCO–10) 66.6 MHz 1/(tCH+tCL) 83.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit 1/(tS+tCO) 22.2 MHz 1/(tS+tCO–10) 28.5 MHz 1/(tCH+tCL) 40.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) Symbol fMAXA Slew Rate Maximum Frequency External Feedback 1/(tSA+tCOA) 38.4 MHz 1/(tSA+tCOA–10) 62.5 MHz 1/(tCHA+tCLA) 71.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 78. Input Macrocell Timing (Product Term Clock) t INH t INL PT CLOCK t IS t IH INPUT OUTPUT t INO AI03101 Table 129. Input Macrocell Timing (5V Devices) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Unit tIS Input Setup Time (Note 1) 0 tIH Input Hold Time (Note 1) 15 tINH NIB Input High Time (Note 1) 9 ns tINL NIB Input Low Time (Note 1) 9 ns tINO NIB Input to Combinatorial Delay (Note 1) ns + 10 34 +2 + 10 ns ns www.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 131. Program, WRITE and Erase Times (5V Devices) Symbol Parameter Min. Flash Program Typ. 8.5 Flash Bulk Erase(1) (pre-programmed) 3 Flash Bulk Erase (not pre-programmed) 5 tWHQV3 Sector Erase (pre-programmed) 1 tWHQV2 Sector Erase (not pre-programmed) 2.2 tWHQV1 Byte Program 14 Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Max. s 30 s s 30 s s 150 100,000 Sector Erase Time-out Unit µs cycles 100 µs (2) 30 ns Max.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 79. Peripheral I/O READ Timing ALE ADDRESS A/D BUS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) tRHQZ (PA) RD tDVQV (PA) DATA ON PORT A AI06610 Table 133. Port A Peripheral Data Mode READ Timing (5V Devices) Symbol Parameter Conditions Min Max Turbo Off Unit 37 + 10 ns 27 + 10 ns www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 80. Peripheral I/O WRITE Timing ALE A / D BUS ADDRESS DATA OUT tWLQV tWHQZ (PA) (PA) WR tDVQV (PA) PORT A DATA OUT AI06611 Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices) Symbol Parameter tWLQV–PA WR to Data Propagation Delay tDVQV–PA Data to Port A Data Propagation Delay tWHQZ–PA WR Invalid to Port A Tri-state Conditions Min (Note 1) Max Unit 25 ns 22 ns 20 ns Max Unit 42 ns 38 ns 33 ns Note: 1.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 81. Reset (RESET) Timing VCC VCC(min) tNLNH-PO Power-On Reset tOPR tNLNH tOPR Warm Reset RESET AI07437 Table 137. Reset (RESET) Timing (5V Devices) Symbol Parameter tNLNH RESET Active Low Time(1) tNLNH–PO Power-on Reset Active Low Time tOPR RESET High to Operational Device Conditions Min Max Unit 150 ns 1 ms 120 ns Max Unit Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. Table 138.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 82. ISC Timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 141. ISC Timing (5V Devices) Symbol Parameter Conditions Min www.BDTIC.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 142.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 85. External Clock Cycle Figure 86. Recommended Oscillator Circuits Note: C1, C2 = 30pF ± 10pF for crystals For ceramic resonators, contact resonator manufacturer Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. www.BDTIC.com/ST Figure 87.
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uPSD3212A, uPSD3212C, uPSD3212CV PACKAGE MECHANICAL INFORMATION Figure 89. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Outline D D1 D2 A2 e E2 E1 E Ne b N 1 A Nd CP L1 www.BDTIC.com/ST c QFP-A A1 α L Note: Drawing is not to scale.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 144. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – – 1.75 – – 0.069 A1 – 0.05 0.020 – 0.002 0.008 A2 – 1.25 1.55 – 0.049 0.061 b – 0.02 0.04 – 0.007 0.016 c – 0.07 0.23 – 0.002 0.009 D 12.00 – – 0.473 – – D1 10.00 – – 0.394 – – E 12.00 – – 0.473 – – E1 10.00 – – 0.394 – – e 0.65 – – 0.026 – – L – 0.45 0.75 – 0.018 0.
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 90. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Outline D D1 D2 A2 e E2 E1 E Ne b N 1 A Nd CP L1 www.BDTIC.com/ST c QFP-A A1 α L Note: Drawing is not to scale.
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uPSD3212A, uPSD3212C, uPSD3212CV Table 145. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – – 1.60 – – 0.063 A1 – 0.05 0.15 – 0.002 0.006 A2 1.40 1.35 1.45 0.055 0.053 0.057 b 0.22 0.17 0.27 0.009 0.007 0.011 c – 0.09 0.20 – 0.004 0.008 D 14.00 – – 0.551 – – D1 12.00 – – 0.472 – – D2 9.50 – – 0.374 – – E 14.00 – – 0.551 – – E1 12.00 – – 0.472 – – E2 9.50 – – 0.
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uPSD3212A, uPSD3212C, uPSD3212CV PART NUMBERING Table 146. Ordering Information Scheme Example: uPSD 3 2 1 2 C V – 24 U 6 T Device Type uPSD = Microcontroller PSD Family 3 = 8032 core PLD Size 2 = 16 Macrocells SRAM Size 1 = 2K bytes Main Flash Memory Size 2 = 64K bytes IP Mix A = USB, I2C, PWM, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) C = I2C, PWM, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) www.BDTIC.com/ST Operating Voltage blank = VCC = 4.5 to 5.
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uPSD3212A, uPSD3212C, uPSD3212CV REVISION HISTORY Table 147. Document Revision History Date Version Revision Details 18-Dec-2002 1.0 First Issue 04-Mar-03 1.1 Updates: port information (Table 30); interface information (Figure 30, Table 44); remove programming guide; PSD Module information (Table 82); PLD information (Figure 55); electrical characteristics (Table 114, 115, 131, 132) 02-Sep-03 1.2 Update references for Product Catalog 03-Feb-04 2.
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uPSD3212A, uPSD3212C, uPSD3212CV www.BDTIC.com/ST Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.