Data Sheet

SPBTLE-1S
P a g e | 10 Rev. 0.1
Module
Pin #
Module Pin Name BlueNRG-1 Function
Pin
(CSP package)
Mode:
“000”
Mode: “001” Mode:
“100”
Mode: “010”
1
ADC2 D5 ADC input 2
2
ADC1 B4 ADC input 1
3
DIO4 C3 GPIO4 UART_RXD I2C2_CLK PWM0
4
DIO5 C2 GPIO5 UART_TXD I2C2_DAT PWM1
5
Vin A3, E6 Supply pin
6
ANATEST0/
DIO14/
A5 GPIO14 I2C1_CLK SPI_CLK ADC_DATA
7
DIO7/BOOT(*) D2 GPIO7 UART_CTS I2C2_DAT PDM_CLK
8
GND A4, B6, C1, F5 Ground
9
DIO6 D1 GPIO6 UART_RTS I2C2_CLK PDM_DATA
10
DIO8 D3 GPIO8 UART_TXD SPI_CLK PDM_DATA
11
DIO11 E2 GPIO11 UART_RXD SPI_CS1 -
12
DIO9 E1 GPIO9 SWCLK SPI_IN
13
DIO10 F1 GPIO10 SWDIO SPI_OUT
14
ANATEST1 D4 Anatest1
15
DIO0 A2 GPIO0 UART_CTS SPI_CLK -
16
DIO2 A1 GPIO2 PWM0 SPI_OUT PDM_CLK
17
DIO3 B1 GPIO3 PWM1 SPI_IN ADC_CLK
18
DIO1 B2 GPIO1 UART_RTS SPI_CS1 PDM_DATA
19
RESETN B3 Reset Pin
20
DIO12 F2 GPIO12 - I2C1CLK
21
N.C N/A Must be left floating
22
N.C N/A Must be left floating
23
N.C N/A Must be left floating
Table 4: Pin assignment
(*) The pin DIO7/BOOT is monitored by bootloader after power up or hardware Reset and it should be low to
prevent unwanted bootloader activation
The Table 4 provides the association between SPBTLE-1S module pin and the related BlueNRG-1 pin.
Refer to the BlueNRG-1 datasheet for detailed description.