Owner's manual

Quantum Series 140 EHC 204 00sc 140 EHC 208 00sc
42
The 3X registers (3X+1 through 3X+8) contain data and status information for channels 1
through 8. You can only set 3X register bits using ladder logic. This section describes the layout for
the status registers (3X+1 through 3X+8) and defines the bits. Ladder logic examples are provided
in chapter 4, “Programming.”
Table 3-7 3X+1 to 3x+8 Register Bit Settings
Function 1 2 3 45678910111213141516
Counter Disable Start 0
Stop 1
Counter Preset Flag Reset 0
Set 1
Gate Enable Echo Disabled 0
Enabled 1
Counter Invert Off 0
On 1
Counter Input State Low 0
High 1
Quadrature Direction Normal 0
Inverted 1
Count Size 65K 0
16M 1
Counter Max Flag Reset 0
Set 1
Counter Limit Flag Reset 0
Set 1
Counter Zero Flag Reset 0
Set 1
Rate Max Flag Reset 0
Set 1
Rate Limit Flag Reset 0
Set 1
Rate Zero Flag Reset 0
Set 1
K&M Factor Set Reset 0
Set 1
R Factor Set Reset 0
Set 1
Configuration Error OK 0
Flag Error 1
Enable Start/Stop Echo: Bit 16
This bit echoes the setting of the Counter Enable bit set in the channels control register. The
counter enable bit allows the counter to continue to count up or down from its present value. Start-
ing or enabling the counter with this bit will not override the external counter input. Both the exter-
nal input enable and the counter start bit must be enabled for the counter to continue counting. If
either the counter stop bit or the external input enable line are disabled the counter will hold its last
value and stop counting.