Data Sheet

NAU7802 24-bit ADC
Nuvoton Confidential - 22 - Revision 1.7
8.7 Internal Band-Gap Circuit
An internal band-gap establishes accurate operation of the device over a wide temperature
range. No adjustment of the bandgap is necessary. For optimum performance, the NAU7802
makes available a band-gap output pin “VBG” which should be bypassed to ground with a
high quality X7R small value 0.1 uF filter capacitor.
8.8 Reset and Power-down mode
An automatic built-in power-on reset function will reset the NAU7802 after DVDD power becomes
valid. After AVDD power is stable (from external power or from the built-in regulator), reset may also
be initiated at any time using the register control interface. The scope of the register based reset using
register 0x00 bit 0, named “RR” set to 1, is equivalent to the power-on reset.
Power-down standby mode can be selected using the register control interface using register 0x00 bits
2:1, named “PUA” and “PUD” set to 0. This mode shuts down the entire analog portion of the part,
including the 24-bit ADC, voltage regulator, PGA, bandgap reference, and internal RC oscillator (or
external crystal oscillator) to reduce power consumption.
The command and control interface is static and works normally in power-down mode. Power-down
mode can be terminated at any time by changing the register controls to return the device to normal
operating mode, using register 0x00 bits 2:1, named “PUA” and “PUD” set to 1. In this way the
contents of the registers are retained for immediate normal use.
After reset or after resuming normal operating mode after power-down mode, the host should wait
through six cycles of data conversion. This allows the device to stabilize all functions and to flush all
old internal data for a full-accuracy output. This timing is automatically generated by the device for
the DRDY pin and Data Ready device status bit.