Data Sheet

NAU7802 24-bit ADC
Nuvoton Confidential - 17 - Revision 1.7
This process will continue while the Master continues to issue ACK signaling. If the Control Register
Address being indexed inside the NAU7802 reaches the value 0x7F (hexadecimal) and the value for
this register is output, the index will roll over to 0x00. The data bytes will continue to be output until the
master terminates the read operation by issuing a STOP condition.
ACK ACK
START
Device Address[6:0]
= 0101010
REG Addr[7:0]Write Device ID [6:0]
Read
Repeat START
ACK
Read Data[7:0]
of REG “Addr”
Host should not drive ACK right
before host wants to issue STOP.
SCLK
SDIO
1 2 ….. 7 8 9
1 2 ….. 8 9
1 2 ….. 8 9 1 2 ….. 7 8 9
STOP
Figure 7: Single Read Sequence
ACK ACK
START
REG Addr[7:0]Write
Read
Repeat START
ACK
Host
ACK
Read Data[7:0]
of REG “Addr”
Read Data[7:0] of
REG “Addr+2”
Host should not drive ACK right
before host wants to issue STOP.
STOP
SCLK
SDIO
Host
ACK
Read Data[7:0] of
REG “Addr+1"
1 2 ….. 7 8 9
1 2 ….. 8 9 1 2 ….. 8 9 1 2 ….. 8 9
1 2 ….. 8 9 1 2 ….. 7 8 9
Device Address[6:0]
= 0101010
Device Address[6:0]
= 0101010
Figure 8: Burst Read Sequence
8.4 2-Wire Timing
Please see electrical specifications
The NAU7802 is compatible with serial clock speeds defined as “standard mode” with SCLK
0 - 100 kHz, and “fast mode” with SCLK 0 - 400 kHz. At these speeds the total bus line
capacitance load is required to be 400 pF or less.
Open collector drivers are required for the serial interface. Therefore, the bus line rise time is
determined by the total serial bus capacitance and the DVDD pull-up resistors. The NAU7802
defaults to a weak pull up (typical 50 k ohm) for applications with no external pull up resistor.
Register 0x11 bits 5:4 provide other options including a strong internal pull-up (typical 1.6 k
ohm) or no internal pull-up resistor.