Data Sheet

NAU7802 24-bit ADC
Nuvoton Confidential - 12 - Revision 1.7
7.6 DIGITAL SERIAL INTERFACE TIMING
T
STAH
T
STAH
T
STOS
T
STAS
T
SDIOS
T
SDIOH
T
SCKL
T
SCKH
T
RISE
T
FALL
SDIO
SCLK
Figure 7: Two-wire Control Mode Timing
Symbol
Description
min
typ
max
unit
T
STAH
SDIO falling edge to SCLK falling edge hold timing in
START / Repeat START condition
600
-
-
ns
T
STAS
SCLK rising edge to SDIO falling edge setup timing in
Repeat START condition
600
-
-
ns
T
STOS
SCLK rising edge to SDIO rising edge setup timing in
STOP condition
600
-
-
ns
T
SCKH
SCLK High Pulse Width
600
-
-
ns
T
SCKL
SCLK Low Pulse Width
1,300
-
-
ns
T
RISE
Rise Time for all 2-wire Mode Signals
-
-
300
ns
T
FALL
Fall Time for all 2-wire Mode Signals
-
-
300
ns
T
SDIOS
SDIO to SCLK Rising Edge DATA Setup Time
100
-
-
ns
T
SDIOH
SCLK falling Edge to SDIO DATA Hold Time
0
-
600
ns