Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Final
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
6 of 60
© 2021 Dialog Semiconductor
Figures
Figure 1: System Diagram ..................................................................................................................... 3
Figure 2: Hardware Block Diagram ....................................................................................................... 9
Figure 3: Software Block Diagram ......................................................................................................... 9
Figure 4: DA16200MOD 37 pins Pin-out Diagram (Top View) ............................................................ 11
Figure 5: TIS 3D Figure 6: TRP 3D ................................................................................... 19
Figure 7: Power on Sequence ............................................................................................................. 20
Figure 8: Pulse Counter Block Diagram .............................................................................................. 24
Figure 9: QSPI Master Block Diagram ................................................................................................ 26
Figure 10: QSPI Master Timing Diagram (Mode 0) ............................................................................. 26
Figure 11: SPI Master Timing Diagram (Mode 0)................................................................................ 27
Figure 12: SPI Slave Block Diagram ................................................................................................... 28
Figure 13: 8-byte Control Type ............................................................................................................ 28
Figure 14: 4-byte Control Type ............................................................................................................ 28
Figure 15: SPI Slave Timing Diagram ................................................................................................. 30
Figure 16: SDIO Slave Block Diagram ................................................................................................ 31
Figure 17: SDIO Slave Timing Diagram .............................................................................................. 31
Figure 18: I2C Master Timing Diagram ............................................................................................... 32
Figure 19: I2C Slave Timing Diagram ................................................................................................. 34
Figure 20: SD/eMMC Block Diagram .................................................................................................. 35
Figure 21: SD/eMMC Master Timing Diagram .................................................................................... 35
Figure 22: I2S Block Diagram.............................................................................................................. 37
Figure 23: I2S Clock Scheme .............................................................................................................. 37
Figure 24: I2S Timing Diagram ........................................................................................................... 38
Figure 25: Left Justified Mode Timing Diagram................................................................................... 38
Figure 26: Right Justified Mode Timing Diagram ................................................................................ 38
Figure 27: I2S Transmit Timing Diagram ............................................................................................ 39
Figure 28: I2S Receive Timing Diagram ............................................................................................. 39
Figure 29: ADC Control Block Diagram ............................................................................................... 40
Figure 30: 12-bit ADC Timing Diagram ............................................................................................... 40
Figure 31: Antenna Switching Internal Block Diagram ........................................................................ 42
Figure 32: Antenna Switching Timing Diagram ................................................................................... 43
Figure 33: DA16200 UART Block Diagram ......................................................................................... 44
Figure 34: Serial Data Format ............................................................................................................. 44
Figure 35: Receiver Serial Data Sampling Points ............................................................................... 45
Figure 36: UARTTXDOE Output Signal for UART RS-485 ................................................................. 45
Figure 37: UART Hardware Flow Control ............................................................................................ 46
Figure 38: PWM Block Diagram .......................................................................................................... 48
Figure 39: PWM Timing Diagram ........................................................................................................ 48
Figure 40: JTAG Timing Diagram ........................................................................................................ 49
Figure 41: Bluetooth Coexistence Interface ........................................................................................ 50
Figure 42: Application Schematic ........................................................................................................ 52
Figure 43: AAC Module Dimension ..................................................................................................... 53
Figure 44: AAE Module Dimension ..................................................................................................... 53
Figure 45: PCB Land Pattern (Top View) ............................................................................................ 54
Figure 46: PCB Land Pattern (Bottom View)....................................................................................... 54
Figure 47: 4-Layer PCB Example ........................................................................................................ 55
Figure 48: Typical PCB Mounting Process Flow ................................................................................. 56
Figure 49: Reflow Condition ................................................................................................................ 57
Tables
Table 1: Pin Description ...................................................................................................................... 12
Table 2: DA16200MOD Pin Multiplexing ............................................................................................. 14
Table 3: Absolute Maximum Ratings ................................................................................................... 15
Table 4: Recommended Operating Conditions ................................................................................... 15
Table 5: DC Parameters, 1.8 V IO ...................................................................................................... 15