Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
49 of 60
© 2021 Dialog Semiconductor
Table 45: PWM Timing Diagram Description
Time
Description
a
Bus Clock Period × (nCycle High + 1)
b
Bus Clock Period × (nCycle Period + 1)
8.12 Debug Interface
DA16200MOD supports both IEEE Standard 1149.1 JTAG (5-wire) and the low-pin-count ARM SWD
(2-wire, TCLK/TMS) debug interfaces. The SWD protocol can handle the same debug features as
the JTAG.
The JTAG port is an IEEE standard that defines a test access port (TAP) and boundary scan
architecture for digital integrated circuits and provides a standardized serial interface to control the
associated test logic. For detailed information on the operation of the JTAG port and TAP controller,
see [4].
Figure 40 shows the JTAG timing diagram.
Figure 40: JTAG Timing Diagram
Table 46 shows the JTAG timing parameters.
Table 46: JTAG Timing Parameters
Parameter Number
Parameter
Parameter Name
Min
Max
Unit
J1
f
TCK
Clock Frequency
15
MHz
J2
t
TCK
Clock Period
1/f
TCK
ns
J3
t
CL
Clock Low Period
t
TCK
/2
ns
J4
t
CH
Clock High Period
t
TCK
/2
ns
J7
t
TMS_SU
TMS Setup Time
1
J8
t
TMS_HO
TMS Hold Time
16
J9
t
TDI_SU
TDI Setup Time
1
J10
t
TDI_HO
TDI Hold Time
16
J11
t
TDO_HO
TDO Hold Time
15