Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
48 of 60
© 2021 Dialog Semiconductor
8.11 PWM
Pulse Width Modulation (PWM) is a modulation technique used to encode a message into a pulse
signal. The blocks are designed to adjust output pulse duration by the CPU bus clock (HCLK).
Figure 38 shows the structure of the PWM block.
AHB
Bus
Matrix
PWM OUT
PWM Block 0
Counter (Period)
Register
Counter (High Duty)
PWM Block 1
Counter (Period)
Register
Counter (High Duty)
PWM Block 2
Counter (Period)
Register
Counter (High Duty)
PWM Block 3
Counter (Period)
Register
Counter (High Duty)
PWM OUT
PWM OUT
PWM OUT
HCLK
Counter
Register
AHB Bus
Figure 38: PWM Block Diagram
Table 44 shows the pin definition of the PWM interface. GPIOx means that PWM signals can go out
through any GPIO pins via register setting.
Table 44: PWM Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOx
PWM[3:0] output
8.11.1 Timing Diagram
Table 45 shows the relation between the internal bus clock and PWM output wave patterns. Figure
39 show the conversion timing diagram. ‘a’ and ‘b’ can be adjusted through the register setting, and
PWM wave patterns vary depending on the ratio. ‘a’ controls the high width of pulses (nCycle High),
while ‘b’ controls the general cycle (nCycle Period).
PWM
a
b
BUS CLK
Figure 39: PWM Timing Diagram