Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
47 of 60
© 2021 Dialog Semiconductor
Table 42: UART Interrupt Signals
Signal Name
Description
UARTMSINTR
UART Modem Status Interrupt
UARTRXINTR
UART Receive FIFO Interrupt
UARTTXINTR
UART Transmit FIFO Interrupt
UARTRTINTR
UART Receive Timeout Interrupt
UARTEINTR
UART Error Interrupt
UARTINTR
UART Interrupt. Five Interrupt signals are combined by OR function
8.10.6 DMA Interface
DA16200MOD UART block can generate DMA request signals with register settings by using DMA
interrupt generator module to connect to DA16200 DMA Controller (DMA1). DMA operation of the
UART is controlled using DMA Control Register.
DA16200MOD UART provides four DMA signals and receives two DMA signals, two signals to
transmit (TXDMASREQ, TXDMABREQ) which are cleared by TX clear signal (TXDMACLR) and two
signals to receive (RXDMASREQ, RXDMABREQ), which are cleared by RX clear signal
(RXDMACLR).
When the DMA interface is not used, the TXDMACLR and RXDMACLR lines should be connected to
a logic ‘0’.
Table 43 shows the pin definition of the UART interface.
Table 43: UART Pin Configuration
Pin Name
Pin Number
I/O
Function Name
UART0_RXD
13
I
UART0_RXD
UART0_TXD
12
O
UART0_TXD
GPIOA7
26
I
UART1_RXD
GPIOA5
28
I
GPIOA3
30
I
GPIOA1
32
I
GPIOA6
27
O
UART1_TXD
GPIOA4
29
O
GPIOA2
31
O
GPIOA0
33
O
GPIOA5
28
I
UART1_CTS
GPIOA4
29
O
UART1_RTS
GPIOA11
22
I
UART2_RXD
GPIOC7
10
I
GPIOA10
23
O
UART2_TXD
GPIOC6
11
O