Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
46 of 60
© 2021 Dialog Semiconductor
Then, generated baud rate divider is 5 + 27/64 = 5.422.
Finally, generated baud rate becomes (8 x 107) / (16 x 5.422) = 922169.
And the error between required baud rate and generated baud rate is
(922169 – 921600) / 921600 x100 = 0.062%.
8.10.4 Hardware Flow Control
Hardware flow control feature is fully selectable, and serial data flow is controlled by using
nUARTRTS output and nUARTCTS input signals. Figure 37 shows how two different UART can
communicate using hardware flow control.
Figure 37: UART Hardware Flow Control
When RTS flow control is enabled, nUARTRTS signal is asserted until the receive FIFO is filled up to
programmed level. When CTS flow control is enabled, transmitter can transmit the data when
nUARTCTS signal is asserted. CTSEn (CTS enable) and RTSEn (RTS enable) bits are determined
by 14th (RTS) and 15th bit (CTS) of UARTCR register.
Table 41: Control bits to enable and disable hardware flow control
CTSEn
RTSEn
Description
1
1
Both RTS and CTS flow control are enabled
1
0
Only CTS flow control is enabled
0
1
Only RTS flow control is enabled
0
0
Both RTS and CTS flow control are disabled
8.10.5 Interrupts
DA16200MOD UART block provides five interrupt signals by separate interrupt lines. Each interrupt
conditions are Modem Status, Receive FIFO Request, Transmit FIFO Request, Receive Timeout and
Reception Error. These conditions are logically OR'ed to provide a single combined interrupt,
UARTINTR. Table 42 shows the interrupt signals.