Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
45 of 60
© 2021 Dialog Semiconductor
An additional parity bit may be added to the serial character. This bit appears between the last data
bit and the stop bit(s) in the character structure. It provides the UART with the ability to perform
simple error checking on the received data.
The UART Line Control Register is used to control the serial character characteristics. The individual
bits of the data word are sent after the start bit, starting with the least significant bit (LSB). These are
followed by the optional parity bit, followed by the stop bit(s), which can be 1 or 2.
Serial Data In
8 16 16
Start Data Bit 0 (LSB) Data Bit 1
Figure 35: Receiver Serial Data Sampling Points
All the bits in the transmission are transmitted for exactly the same time duration. This is referred to
as a Bit Period or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line, the
receiver samples the serial input data at approximately the mid-point of the Bit Time, once the start
bit has been detected. As the exact number of baud clocks that each bit was transmitted for is
known, calculating the mid-point for sampling is not difficult, that is every 16 baud clocks after the
mid-point sample of the start bit. Figure 35 shows the sampling points of the first couple of bits in a
serial character.
8.10.2 RS-485
DA16200MOD UART supports RS-485. UART485EN register (0x054) is required to be assigned to
one to enable the RS-485. In order to use RS-485, additional signal (UARTTXDOE) is required to
notice TXD intervals. This signal can be an output by selecting any unused pins among the GPIO
pins.
Figure 36: UARTTXDOE Output Signal for UART RS-485
8.10.3 Baud Rate
UART clock frequency (FUARTCLK) is fixed to 80 MHz. Baud Rate Divisor can be calculated as
(FUARTCLK / (16 x Baud Rate)). Baud Rate Divisor is comprised of the integer part
(UART_INTBRDIV) and fractional part (UART_FRABRDIV). The maximum baud rate of DA16200
UART is 2.5 MBaud.
The following example shows how to calculate the divisor value.
Example:
If the required baud rate is 921600 with 80 MHz FUARTCLK, the Baud Rate Divisor becomes
(8 x 107) / (16 x 921600) = 5.425.
This means the integer value is 5 and the fractional value is 0.425.
Then, the fraction part becomes integer ((0.425 x 64) + 0.5) = 27.