Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagram
- Contents
- Figures
- Tables
- 1 Terms and Definitions
- 2 References
- 3 Block Diagram
- 4 Pinout
- 5 Electrical Specification
- 6 Power Management
- 7 Core System
- 8 Peripherals
- 9 Applications Schematic
- 10 Package Information
- 11 Ordering Information
- Revision History
DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
43 of 60
© 2021 Dialog Semiconductor
Figure 32: Antenna Switching Timing Diagram
For reference, this antenna switching diversity is different from MRC. (Maximum Ratio Combining)
8.10 UART
DA16200MOD provides 3 UARTs, features of which are described below:
● Programmable use of UART (UART1 and UART2)
● Compliance to the AMBA AHB bus specification [6] for easy integration into SoC implementation
● Supports both byte and word access for reduction of bus burden
● Supports both RS-232 and RS-485
● Separate 32×8 bit transmit and 32×12 bit receive FIFO memory buffers to reduce CPU interrupts
● Programmable FIFO disabling for 1-byte depth
● Programmable baud rate generator
● Standard asynchronous communication bits (start, stop and parity), which are added prior to
transmission and removed on reception
● Independent masking of transmit FIFO, receive FIFO, and receive timeout
● Supports for DMA
● False start bit detection
● Programmable flow control (CTS/RTS, UART1)
● Fully programmable serial interface characteristics:
○ Data can be of 5,6,7, or 8 bits
○ Even, odd, stick, or no-parity bit generation and detection
○ 1- or 2- stop bit generation
○ Baud rate generation