Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
40 of 60
© 2021 Dialog Semiconductor
ADC
12b
Max : 1Ms
Counter
16-bit
ADC Controller
Ready
CH_SEL
SWITCH
VI_N[1]
VI_N[2]
VI_N[3]
VI_N[4]
Switch
Figure 29: ADC Control Block Diagram
8.8.2 Timing Diagram
The input is digitized at a maximum of 1.0 Msps throughput rate. And the maximum input clock rate
is 15 MHz.
Figure 30 shows the conversion timing, and Table 39 describes DC specifications.
Figure 30: 12-bit ADC Timing Diagram
Table 39: DC Specification
Description
Min
Typ
Max
Unit
Resolution
4
12
12
Bits
Max clock input
15
MHz
Conversion frequency
1
MHz
Accuracy:
● SNR
● SNDR
● 61.7
● 67.2
● dB
● dB
Analog input range
0
1.4
V
8.8.3 DMA Transfer
There are four ADC channel settings available. Once the input data of each channel reaches the
FIFO level, it is possible to read the data through the DMA path.
CLK
15MHz
SAMPLE
1M
CLKOUT
1M
AUXADC_EN
OSC_EN
D<11:0>
15*CLK
N
15*CLK
N+1
15*CLK
N+2
15*CLK
N+3
15*CLK
N+4
N
N+1
N+2
N+3
15*CLK