Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
39 of 60
© 2021 Dialog Semiconductor
I2S_BCLK
I2S_SDO
(falling edge)
T
5
T
4
T
2
T
3
f
BCLK
I2S_SDO
(rising edge)
Figure 27: I2S Transmit Timing Diagram
T
5
T
4
T
2
T
3
f
BCLK
I2S_BCLK
I2S_SDO
Figure 28: I2S Receive Timing Diagram
Table 37: I2S Transmit Timing Parameters
Description
Timing
Min
Typ
Max
Unit
I2S_BCLK frequency
f
BCLK
-
3.072
MHz
High period of the BCLK clock
T
2
-
½ f
BCLK
ns
Low period of the BCLK clock
T
3
-
½ f
BCLK
ns
I2S_SDO output hold (falling edge)
T
4
160
-
ns
I2S_SDO output hold (rising edge)
T
5
160
-
ns
Table 38: I2S Receive Timing Parameters
Description
Timing
Min
Typ
Max
Unit
I2S_BCLK frequency
f
BCLK
-
3.072
MHz
High period of the BCLK clock
T
2
-
½ f
BCLK
ns
Low period of the BCLK clock
T
3
-
½ f
BCLK
ns
I2S_SDO input setup time
T
4
15
-
ns
I2S_SDO input hold time
T
5
60
-
ns
8.8 ADC (Aux 12-bit)
8.8.1 Overview
DA16200MOD includes a high precision, ultra-low power, and wide dynamic range SAR ADC with a
12-bit resolution. It has a 4-channel single-end ADC.
Analog input is measured by four pins from GPIOA0 to GPIOA3, and pin selection is changed
through the register setting.
Figure 29 shows the control block diagram.