Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
38 of 60
© 2021 Dialog Semiconductor
Table 36: I2S Clock Selection Guide
Parameter
Units
LRCK
Fs
8
12
16
24
32
44.1
46.875
48
KHz
BCLK
64Fs
0.512
0.768
1.024
1.536
2.048
2.8224
3
3.072
MHz
MCLK
512Fs
4.096
6.144
8.192
12.288
16.384
22.5792
24
24.576
MHz
Clk Div2
N
(=1,2,3…)
6
4
3
2
2
1
1
1
I2S_CLK
24.576
24.576
24.576
24.576
32.768
22.5792
24
(Internal
PLL)
24.576
MHz
NOTE
To confirm the exact LRCK operation, drive the Clock source at I2S_CLK.
8.7.3 I2S Transmit and Receive Timing Diagram
I2S output is possible in the following three modes. The main clock (MCLK) always outputs in 512×fs.
● I2S Mode
LRCK
SCLK
SDATA
MSB
-1
-2 -3 +3 +2
+1
LSB
MSB
-1
-2 -3 -4 +3 +2
+1
LSB
Left Channel
Right Channel
Figure 24: I2S Timing Diagram
● Left Justified Mode
LRCK
SCLK
SDATA
MSB
-1
-2 -3 +3 +2
+1
LSB
MSB
-1
-2 -3 -4 +3 +2
+1
LSB
Left Channel
Right Channel
Figure 25: Left Justified Mode Timing Diagram
● Right Justified Mode
LRCK
SCLK
SDATA
15
14
2 1 0
Left Channel
Right Channel
13
15
14
2 1 0
13
Figure 26: Right Justified Mode Timing Diagram