Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagram
- Contents
- Figures
- Tables
- 1 Terms and Definitions
- 2 References
- 3 Block Diagram
- 4 Pinout
- 5 Electrical Specification
- 6 Power Management
- 7 Core System
- 8 Peripherals
- 9 Applications Schematic
- 10 Package Information
- 11 Ordering Information
- Revision History
DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
37 of 60
© 2021 Dialog Semiconductor
8.7.1 Block Diagram
I2S has the following features:
■ Master Clock Mode only
■ I2S Data pin can work in either input mode or output mode
■ Clock source can be "internal 480 MHz/N" (currently using 24 MHz) or "external clock source"
■ Max Sampling Rate: 48 KHz
■ Mono/Stereo Mode
Figure 22: I2S Block Diagram
8.7.2 I2S Clock Scheme
The I2S uses a 24 MHz clock as default from the RF reference clock (40 MHz), so it can support
46.875 KHz of sampling rate. External clock sources are needed to support the standard sampling
rate. See Table 36.
Figure 23: I2S Clock Scheme