Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
36 of 60
© 2021 Dialog Semiconductor
Table 34 lists the timing parameters for the SD/eMMC master.
Table 34: SD/eMMC Master Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
SD/eMMC_CLK frequency
F
SCLK
-
-
50
MHz
SD/eMMC_CLK clock duty
50
%
SD/eMMC_CMD input setup time
T
CI.SU
8
ns
SD/eMMC_CMD output delay time
T
CO.DLY
3
ns
SD/eMMC_D[3:0] input setup time
T
DI.SU
8
ns
SD/eMMC_D[3:0] output delay time
T
DO.DLY
8
ns
8.7 I2S
DA16200MOD provides an I2S interface. Once an I2S block receives audio data through the DMA, it
sends audio data to the external port according to the I2S standard. To use the external DAC, output
through the GPIO port is possible through the register setting according to the pin configuration
(Table 35).
The I2S also provides a receive function. However, I2S transmission and reception functions cannot
be used at the same time. The transmit and receive functions can be selected by register setting. If
the I2S signal is input from outside after the reception function is set, the audio signal can be
decoded, stored in the FIFO, and read out through the DMA. The decodable reception function
provides 8/16/24/32-bit modes and can receive either mono or stereo.
Using the I2S clock divider register, the internal PLL clock can be variably applied to the I2S clock
source. The available I2S clock source is 24/48 MHz. There is also a way to apply the I2S clock
source directly from outside using the GPIO pin. For accurate I2S audio sampling, I2S clock source
can be input to external GPIO pins. It needs to select the GPIO pin setting as the I2S clock input and
apply appropriate clock source. The available I2S clock pins are shown in Table 35.
Table 35: I2S Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOA1
32
O
I2S_MCLK
GPIOA5
28
O
GPIOA9
24
O
GPIOA0
33
O
I2S_BCLK
GPIOA4
29
O
GPIOA8
25
O
GPIOA3
30
O
I2S_LRCK
GPIOA7
26
O
GPIOA2
31
I/O
I2S_SDO
GPIOA6
27
I/O
GPIOA3
30
I
I2S_CLK_IN
GPIOA10
23
I