Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
35 of 60
© 2021 Dialog Semiconductor
8.6 SD/SDeMMC
The SD/eMMC host IP provides the function for DA16200MOD to access SD or eMMC cards. This
SD/eMMC host IP only supports a 4-bit data bus and the maximum clock rate is 50 MHz. The
maximum data rate is 25 MB/s (200 Mbps) under the 4-bit data bus and 50 MHz clock.
SD/eMMC pin mux condition is defined in Table 33.
Table 33: SD/eMMC Master Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOA4
29
I/O
SD/eMMC_CMD
GPIOA5
28
O
SD/eMMC_CLK
GPIOA9
24
I/O
SD/eMMC_D0
GPIOA8
25
I/O
SD/eMMC_D1
GPIOA7
26
I/O
SD/eMMC_D2
GPIOA6
27
I/O
SD/eMMC_D3
GPIOA10
23
I
SD/eMMC_WRP
GPIOA1
32
I
8.6.1 Block Diagram
Figure 20 shows the block diagram of SD/eMMC host IP and it includes the control register, clock
control, command/response pipe, data pipe, and AHB master interface blocks.
AHB
Slave
Control
Registers
Data
Pipe
AHB
Master
32
32
Clock
Control
HCLK
HCMD
HDATA[3:0]
4
CMD/RSP
Pipe
AHB
FIFO
32
Figure 20: SD/eMMC Block Diagram
Figure 21 shows the timing diagram for the SD/eMMC master.
SD/eMMC_CLK
SD/eMMC_D[3:0]
SD/eMMC_CMD
T
CO.DLY
T
DO.DLY
T
CI.SU
T
DI.SU
Figure 21: SD/eMMC Master Timing Diagram