Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
34 of 60
© 2021 Dialog Semiconductor
Figure 19 shows the I2C slave timing diagram.
T
HD;STA
S
SDA
SCL
T
R
T
SU;DAT
T
HIGH
T
LOW
T
R
T
HD;DAT
T
VD;ACK
cont.
...
...
SDA
SCL
cont.
...
...
T
SU;STA
T
HD;STA
S
r
T
BUF
P
T
SU;STO
S
Figure 19: I2C Slave Timing Diagram
Table 32 lists the I2C slave timing parameters.
Table 32: I2C Slave Timing Parameters
Parameter
Symbol
Fast Mode
High Speed Mode
Unit
Min
Max
Min
Max
SCL clock frequency
F
SCLK
0
400
0
1000
(Note 2)
kHz
Clock Duty (Note 1)
40
60
40
60
%
Hold time of START
T
HD;STA
0.6
-
0.26
-
μs
Low period of the SCL clock
T
LOW
1.3
-
0.5
-
μs
High period of the SCL clock
T
HIGH
0.6
-
0.26
-
μs
Setup time for START condition
T
SU;STA
0.6
-
0.26
-
μs
Data hold time
T
HD;DAT
0
-
0
-
μs
Data setup time
T
SU;DAT
100
-
50
-
ns
Rise time of both SDA and SCL
T
R
20
300
-
120
ns
Setup time for STOP condition
T
SU;STO
0.6
-
0.26
-
μs
Data valid acknowledge time
T
VD;ACK
-
-
-
-
μs
Buffer free time between
START and STOP condition
T
BUF
1.3
-
0.5
-
μs
Note 1 Clock duty ratio = (T
HIGH
/T
SCLK
) × 100[%], TSCLK = 1/FSCLK
Note 2 Max. clock = 1.0 MHz (clock period = 1000 ns)