Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
32 of 60
© 2021 Dialog Semiconductor
Parameter
Symbol
Min
Typ
Max
Unit
SDIO_CMD output delay time
T
CO.DLY
11 (Note 1)
ns
SDIO_D[3:0] input setup time
T
DI.SU
3
ns
SDIO_D[3:0] output delay time
T
DO.DLY
11 (Note 1)
ns
Note 1 SDIO signals can set previous output from half cycle.
8.5 I2C Interface
8.5.1 I2C Master
DA16200MOD includes an I2C master module. Three ranges of clock speed are supported: standard
(100 kHz), fast (400 kHz), and high (1.0 MHz) speed mode. Table 29 shows the pin definition of the
I2C master interface.
Table 29: I2C Master Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOA1
32
O
I2C_CLK
GPIOA5
28
O
GPIOA9
24
O
GPIOA0
33
I/O
I2C_SDA
GPIOA4
29
I/O
GPIOA8
25
I/O
Figure 18 shows the I2C timing diagram. The timing diagram is the same as that of I2C slave timing
diagram.
T
HD;STA
S
SDA
SCL
T
R
T
SU;DAT
T
HIGH
T
LOW
T
R
T
HD;DAT
T
VD;ACK
cont.
...
...
SDA
SCL
cont.
...
...
T
SU;STA
T
HD;STA
S
r
T
BUF
P
T
SU;STO
S
Figure 18: I2C Master Timing Diagram
Table 30 lists the I2C master timing parameters.
Table 30: I2C Master Timing Parameters
Parameter
Symbol
Fast Mode
High Speed Mode
Unit
Min
Max
Min
Max
Bus clock frequency
F
op_clk
30
160
30
160
MHz