Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
31 of 60
© 2021 Dialog Semiconductor
Command
Decoder
APB bus
Interface
REG.
Control
Fn0 / Fn1
Decoder
DAT
Decoder
Response
Generator
CRC
Generator
2 port
Memory
DMA
Controller
Figure 16: SDIO Slave Block Diagram
Table 27 shows the pin definition of the SDIO interface.
The GPIOA4 and GPIOA5 pins are set to SDIO CMD and CLK by default. If SDIO initialization is
performed and SDIO communication is enabled, SDIO data pin setting is performed automatically. In
other words, when the SDIO communication is detected, the pin used as the SDIO data among the
GPIO pins is automatically activated in the SDIO use mode. However, the auto setting function is not
supported for the F_xxx pin used as the flash function.
Table 27: SDIO Slave Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOA4
29
I/O
SDIO_CMD
GPIOA5
28
I
SDIO_CLK
GPIOA9
24
I/O
SDIO_D0
GPIOA8
25
I/O
SDIO_D1
GPIOA7
26
I/O
SDIO_D2
GPIOA6
27
I/O
SDIO_D3
Figure 17 shows the timing diagram for the SDIO slave.
SDIO_CLK
SDIO_D[3:0]
SDIO_CMD
T
CO.DLY
T
DO.DLY
T
CI.SU
T
DI.SU
Figure 17: SDIO Slave Timing Diagram
Table 28 lists the timing parameters for the SDIO slave.
Table 28: SDIO Slave Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
SDIO_CLK frequency
F
SCLK
-
-
50
MHz
SDIO_CLK clock duty
50
%
SDIO_CMD input setup time
T
CI.SU
3
ns