Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
30 of 60
© 2021 Dialog Semiconductor
SPI_CSB
SPI_CLK
(CPOL=0)
SPI_MOSI
SPI_MISO
T
SCLKL
T
MSU
T
MHD
T
SSU
MSB LSB
LSB
T
SCLKH
T
SCLKOFF
T
SCLKON
T
TR
T
CSBOFF
SPI_CLK
(CPOL=1)
T
SCLKL
T
SCLKH
Figure 15: SPI Slave Timing Diagram
Table 26 lists the timing parameters for the SPI slave.
Table 26: SPI Slave Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
SCLK frequency
F
SCLK
-
-
50
MHz
SCLK clock duty
40
%
Non active duration
T
SCLKOFF
400
-
-
ns
1st CLK active rising transition time
T
SCLKON
T
SCLKL
(CPOL=0)
T
SCLKH
(CPOL=1)
-
-
ns
CSB non active rising transition time
T
CSBOFF
T
SCLKH
(CPOL=0)
T
SCLKL
(CPOL=1)
-
-
ns
MOSI setup time
T
MSU
8
-
T
SCLK
(Note 1)
ns
MOSI hold time
T
MHD
8
-
T
SCLK
ns
MISO delay time
T
SSU
-
-
8
ns
MISO transition time(10% to 90% transition)
T
TR
-
4
5
ns
Note 1 T
SCLK
= 0.5 × (F
SCLK
x 10
6
)
-1
second
8.4 SDIO
SDIO is a full/high speed card suitable for memory card and I/O card applications with low power
consumption. The full/high speed card supports SPI, 1-bit SD, and 4-bit SD transfer modes at the full
clock range of 0 to 50 MHz. To be compatible with the serviceable SDIO clock, the internal BUS
clock needs to be set to minimum 50 MHz. The CIS and CSA area is located inside the internal
memory and the SDIO registers(CCCR and FBR) are programmed by the SD host.