Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
28 of 60
© 2021 Dialog Semiconductor
Table 22: SPI Master Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
QSPI_CLK frequency
F
CLK
5
60
MHz
QSPI_CLK clock duty
50
%
1st CLK active rising transition time
T
CLK.ON
0.5 × T
CLK
T
CLK
(Note 1)
ns
QSPI_CSB non-active rising transition time
T
CSB.OFF
0
T
CLK
ns
QSPI_D[3:0] input setup time
T
DI.SU
6
ns
QSPI_D[3:0] output delay time
T
DO.DLY
2
ns
Note 1 T
CLK
= (F
CLK
× 10
6
)
-1
seconds
8.3 SPI Slave
SPI slave interface supports the control of DA16200 by an external host. The range of SPI clock
speed is the same as that of the internal bus clock speed. The SPI slave supports both the burst
mode and non-burst mode. In the burst mode, SPI_CSB remains active from the start to the end of
communication. In the non-burst mode, SPI_CLK remains active at every eight bits.
SPI Signals
Address
Decoder
Command
Decoder
Data
Decoder
APB bus
Controller
Figure 12: SPI Slave Block Diagram
Communication protocols of the SPI slave interface use either 4-byte or 8-byte control signals.
Between the two available communication protocols, the CPU chooses one before initiating the
control.
Figure 13 and Figure 14 shows the 8-byte and 4-byte control types.
SPI_CSB
SPI_CLK
SPI_MOSI
A [ 31 : 24 ]
A [ 7 : 0 ]
A [ 15 : 8 ]
A [ 23 : 16 ]
C [ 7 : 0 ] L [ 23 : 16 ]
L [ 15 : 8 ]
L [ 7 : 0 ]
D [ 7 : 0 ] D [ 15 : 8 ]
D [ 23 : 16 ]
D [ 31 : 24 ]
Figure 13: 8-byte Control Type
SPI_CSB
SPI_CLK
SPI_MOSI
A [ 15 : 8 ]
L [ 7 : 0 ]
C [ 7 : 0 ]
A [ 7 : 0 ]
D [ 7 : 0 ] D [ 15 : 8 ]
D [ 23 : 16 ]
D [ 31 : 24 ]
Figure 14: 4-byte Control Type