Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
27 of 60
© 2021 Dialog Semiconductor
Table 20 lists the timing parameters for the QSPI master.
Table 20: QSPI Master Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
QSPI_CLK frequency
F
CLK
10
120
MHz
QSPI_CLK clock duty
50
%
1st CLK active rising transition time
T
CLK.ON
0.5 ×T
CLK
T
CLK
(Note 1)
ns
QSPI_CSB non-active rising transition time
T
CSB.OFF
0
T
CLK
ns
QSPI_D[3:0] input setup time
T
DI.SU
6
ns
QSPI_D[3:0] output delay time
T
DO.DLY
2
ns
Note 1 T
CLK
= (F
CLK
× 10
6
)
-1
seconds
8.2 SPI Master
QSPI can use the SPI master by means of single line interface. Table 21 shows the pin definition of
the SPI master interface. SPI signal timing is the same as QSPI.
To use DA16200MOD as an SPI master, the CSB signal can be used with any of the GPIO pins.
CSB [3:1] can be selected from GPIO special function by setting the registers in the GPIO.
Table 21: SPI Master Pin Configuration
Pin Name
Pin Number
I/O
Function Name
GPIOx
O
E_SPI_CSB[3:1]
GPIOA6
27
O
E_SPI_CSB[0]
GPIOA7
26
O
E_SPI_CLK
GPIOA8
25
I/O
E_SPI_MOSI or E_SPI_D[0]
GPIOA9
24
I/O
E_SPI_MISO or E_SPI_D[1]
GPIOA10
23
I/O
E_SPI_D[2]
GPIOA11
22
I/O
E_SPI_D[3]
E_SPI_CSB
E_SPI_CLK
E_SPI_D[3:0]
T
CLK.ON
T
DO.DLY
T
DI.SU
T
CSB.OF
F
Figure 11: SPI Master Timing Diagram (Mode 0)