Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagram
- Contents
- Figures
- Tables
- 1 Terms and Definitions
- 2 References
- 3 Block Diagram
- 4 Pinout
- 5 Electrical Specification
- 6 Power Management
- 7 Core System
- 8 Peripherals
- 9 Applications Schematic
- 10 Package Information
- 11 Ordering Information
- Revision History
DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
26 of 60
© 2021 Dialog Semiconductor
I-Cache
Controller
AHB
BusMatrix
AHB
Bus
MS
QSPI
Master
with XIP feature
AHB
Bus
AHB
Bus
S0
S1
External
Serial
NOR Flash
DMA
M
AHB
Bus
XIP path
Configuration
DMA
Figure 9: QSPI Master Block Diagram
Figure 10 shows the timing diagram for the QSPI master.
QSPI_CSB
QSPI_CLK
QSPI_D[3:0]
T
CLK.ON
T
DO.DLY
T
DI.SU
T
CSB.OF
F
Figure 10: QSPI Master Timing Diagram (Mode 0)