Datasheet

DA16200MOD
Ultra Low Power Wi-Fi Module
Datasheet
Revision 3.1
03-Feb-2021
CFR0011-120-00
24 of 60
© 2021 Dialog Semiconductor
Table 19: I/O Power Domain
[25] DIO1
[26] DIO2
[27] FDIO
GPIOA[11:4]
GPIOC[8:6]
F_CLK
TCLK/TMS
F_CSN
UART0_RXD/UART0_TXD
F_IO0 to F_IO3
7.4 Pulse Counter
7.4.1 Introduction
The pulse counter is a module which counts the number of rising or falling edges of input signals.
And this counter module can run even in Sleep mode. It includes one 32-bit up-counter. The input
channel can be chosen by register setting among the 11 digital I/Os. It also has a glitch filter which is
designed to remove the unwanted trigger of an input signal.
7.4.2 Functional Description
Ext.
Pad
Mux.
Mux_SEL
Glitch
Filter
Edge
Select
Counter Int
Gli_En
Gli_Thresh
Edge_Sel
Count_En
Count_Rst
Int_Clr
Int_Thresh
Int
PCLK
Pulse
Edge
Pulse
Count
CLK_32kHz
ㅣ
ㅣ
Figure 8: Pulse Counter Block Diagram
7.4.2.1 Input
Available input channels are described in Table 18. It uses the same input sources with the wake-up
controller. By register setting, input channels can be selected among 11 digital I/Os.
7.4.2.2 Clock
The operation clock of the pulse counter is 32 kHz.
7.4.2.3 Counter
As described in Figure 8, the pulse counter is activated by several counter control signals. By register
setting, input signals can be selected on either the rising edges or falling edges. In order to enable
the glitch filter module, Gli_En and Gli_Thresh register values need to be set. The pulses whose
cycles are shorter than the Gli_Thresh value are removed. The counter is a 32-bit up-counter and the
counter value can be reset to zero by Count_Rst.
7.4.2.4 Interrupts
An interrupt occurs when the counter values reaches the Interrupt Threshold value (Int_Thresh). In
Sleep mode, this interrupt can be used as a wake-up source.