Datasheet

ManualsBrandsSparkfun Electronics ManualsData Communication and Human Input DevicesSparkFun Qwiic WiFi Shield - DA16200

Table Of Contents

DA16200MOD

Ultra Low Power Wi-Fi Module

Final

Datasheet

Revision 3.1

03-Feb-2021

CFR0011-120-00

1 of 60

General Description

The DA16200MOD is a fully integrated Wi-Fi

module with ultra-low power consumption, best RF

performance and easy development environment. Such low power operation can extend the battery

life as longer as a year or more depending on the application.

This module series included DA16200-00000A32, 40 MHz crystal oscillator, 32.768 KHz RTC clock,

RF Lumped RF filter, 4 M-byte flash memory and chip antenna or u.FL connector. The

DA16200MOD has chip antenna type (DA16200MOD-AAC4WA32) and u.FL connector type

(DA16200MOD-AAE4WA32) for external antenna.

The Module is built from the ground up for the Internet of Things (IoT) and is ideal for door locks,

thermostats, sensors, pet trackers, asset trackers, sprinkler systems, connected lighting, video

cameras, video door bells, wearables and other IoT devices.

The modules certified Wi-Fi alliance for IEEE802.11b/g/n, Wi-Fi Direct, WPS functionalities and it has

been approved by many countries including the United States (FCC), Canada (IC) and China

(SRRC). Using the Wi-Fi Alliance transfer policy, the Wi-Fi Certifications can be transferred without

being tested again.

For more information on DA16200MOD, please refer to DA16200-00000A32 datasheet.

Key Features

■ Module variants

□ DA16200MOD-AAC4WA32 (chip Antenna)

□ DA16200MOD-AAE4WA32 (u.FL cont.)

■ Highly integrated ultra-low power Wi-Fi

system module

□ Sleep current: 3.5 uA, VBAT=3.3 V

■ Best RF Performance

□ Tx Power: +19 dBm, 1 Mbps DSSS

□ Rx Sensitivity: -98.5 dBm, 1 Mbps DSSS

■ Full offload: SoC runs full networking OS and

TCP/IP stack

■ Wi-Fi processor

□ IEEE 802.11b/g/n, 1x1, 20 MHz channel

bandwidth, 2.4 GHz

□ IEEE 802.11s Wi-Fi mesh

□ Wi-Fi security: WPA/WPA2-

Enterprise/Personal, WPA2 SI, WPA3

SAE, and OWE

□ Vendor EAP types: EAP-

TTLS/MSCHAPv2, PEAPv0/EAP-

MSCHAPv2, PEAPv1, EAP-FAST, and

EAP-TLS

□ Operating modes: Station, SoftAP, and

Wi-Fi Direct

Modes (GO, GC, GO fixed)

□ WPS-PIN/PBC for easy Wi-Fi provisioning

□ Connection manager for autonomous and

fast Wi-Fi connections

□ Bluetooth coexistence

□ Antenna switching diversity

■ Built-in 4-channel auxiliary ADC for sensor

interfaces

□ 12-bit SAR ADC: single-ended four

channels

□ Provides dynamic auto switching function

■ Supports various interfaces

□ eMMC/SD expanded memory

□ SDIO Host/Slave function

□ QSPI for external flash control

□ Three UARTs

□ SPI Master/Slave interface

□ I2C Master/Slave interface

□ I2S for digital audio streaming

□ 4-channel PWM

□ Individually programmable, multiplexed

GPIO pins

□ JTAG and SWD

■ Wi-Fi Alliance certifications:

□ Wi-Fi CERTIFIED™ b, g, n

□ WPA™ - Enterprise, Personal

□ WPA2™ - Enterprise, Personal

□ WPA3™ - Enterprise, Personal

■ RF Regulatory certifications

□ FCC, IC, CE, KC, TELEC, SRRC

■ CPU core subsystem

□ Arm® Cortex®-M4F core w/ clock

frequency of 30~160 MHz

Summary of content (60 pages)

PAGE 1
DA16200MOD Final Ultra Low Power Wi-Fi Module General Description The DA16200MOD is a fully integrated Wi-Fi® module with ultra-low power consumption, best RF performance and easy development environment. Such low power operation can extend the battery life as longer as a year or more depending on the application. This module series included DA16200-00000A32, 40 MHz crystal oscillator, 32.768 KHz RTC clock, RF Lumped RF filter, 4 M-byte flash memory and chip antenna or u.FL connector.
PAGE 2
DA16200MOD Final Ultra Low Power Wi-Fi Module ■ Hardware accelerators □ General HW CRC engine □ HW zeroing function for fast booting □ Pseudo random number generator □ ROM: 256 KB, SRAM: 512 KB, OTP: 8 KB, Retention Memory: 48 KB (PRNG) ■ Complete software stack □ Comprehensive networking software stack □ Provides TCP/IP stack: in the form of ■ SPI flash Memory □ 32 M-bit / 4 M-byte ■ External Clock source □ 40 MHz crystal (± 25 ppm) for master clock (initial + temp + aging) □ 32.
PAGE 3
DA16200MOD Final Ultra Low Power Wi-Fi Module Applications DA16200MOD is a full offload SoC for IoT Applications, such as: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Security systems Door locks Thermostats Garage door openers Blinds Lighting control Sprinkler systems Video camera security systems Smart appliances Video door bell Asset tracker System Diagram Figure 1: System Diagram Datasheet CFR0011-120-00 Revision 3.
PAGE 4
DA16200MOD Final Ultra Low Power Wi-Fi Module Contents General Description ............................................................................................................................ 1 Key Features ........................................................................................................................................ 1 Applications .........................................................................................................................................
PAGE 5
DA16200MOD Final Ultra Low Power Wi-Fi Module 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 9 QSPI: Master with XIP Feature ........................................................................................... 25 SPI Master .......................................................................................................................... 27 SPI Slave ............................................................................................................................
PAGE 6
DA16200MOD Final Ultra Low Power Wi-Fi Module Figures Figure 1: System Diagram ..................................................................................................................... 3 Figure 2: Hardware Block Diagram ....................................................................................................... 9 Figure 3: Software Block Diagram .........................................................................................................
PAGE 7
DA16200MOD Final Ultra Low Power Wi-Fi Module Table 6: DC Parameters, 3.3 V IO ...................................................................................................... 16 Table 7: DC Parameters for RTC block, 3.3 V VBAT .......................................................................... 16 Table 8: DC Parameters for RTC block, 2.1 V VBAT .......................................................................... 16 Table 9: DC Parameters for Digital Wake-up, 3.3 V VBAT & 1.8/3.3 V IO .
PAGE 8
DA16200MOD Final Ultra Low Power Wi-Fi Module 1 Terms and Definitions API CRC DMA GPIO HW I2C I2S IoT JTAG LDO LLI NVIC NVRAM PLL PRNG PWM QSPI RTC SAR ADC SPI SW SWD UART XIP TAP 2 [1] [2] [3] [4] [5] [6] Application Programming Interface Cyclic Redundancy Check Direct Memory Access General Purpose Input/Output Hardware Inter-Integrated Circuit Inter-IC Sound Internet of Things Joint Test Action Group Low-dropout Regulator Linked-List Item Nested Vectored Interrupt Controller Non-Volatile RAM Phase-l
PAGE 9
DA16200MOD Final Ultra Low Power Wi-Fi Module 3 Block Diagram Figure 2 shows the DA16200MOD hardware (HW) block diagram. VBAT_3V3 VDD_DIO1 VDD_DIO2 Chip Antenna type DA16200MOD-AAC PIN Mux 32.768KHz Crystal Quad-SPI SPI 2.4GHzRF filter & Matching UART GPIOs PWM RTC Control External Antenna type (u.
PAGE 10
DA16200MOD Final Ultra Low Power Wi-Fi Module The following descriptions are about the SW block diagrams.
PAGE 11
DA16200MOD Final Ultra Low Power Wi-Fi Module 4 4.
PAGE 12
DA16200MOD Final Ultra Low Power Wi-Fi Module Table 1: Pin Description #Pin Pin Name Type 1 NC NC NOT CONNECT 2 GND GND RF VDD 3 RTC_PWR_KEY DI RTC block enable signal 4 RTC_WAKE_UP DI RTC block wake-up signal 5 RTC_SENSOR DO Sensor control signal 6 NC NC NOT CONNECT 7 JTAG_TMS DIO 2/4/8/12 I-PU JTAG I/F, SWDIO 8 JTAG_TCLK DIO 2/4/8/12 I-PD JTAG I/F, SWCLK, General Purpose I/O 9 GPIOC8 DIO 2/4/8/12 I-PD General Purpose I/O 10 GPIOC7 DIO 2/4/8/12 I-PD Genera
PAGE 13
DA16200MOD Final Ultra Low Power Wi-Fi Module 4.2 Pin Multiplexing This device provides various interfaces to support many kinds of applications. It is possible to control each pin according to the required application in reference to the pin multiplexing illustrated in Table 2. Pin control can be realized through register setting. This device can use a maximum of 16 GPIO pins and each of the GPIO pins multiplexes signals of various functions.
PAGE 14
DA16200MOD-AA series Ultra Low Power Wi-Fi Module Table 2: DA16200MOD Pin Multiplexing Module default Pin GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8 GPIOA9 GPIOA10 GPIOA11 TCLK/ GPIOA15 TMS UART_TXD UART_RXD GPIOC8 GPIOC7 GPIOC6 Note 1 JTAG GPIO GPIO GPIO GPIO UART1_TXD UART1_RXD WPS Factory_reset GPIO GPIO GPIO GPIO Analog SPI master CH0 CH1 CH2 CH3 SPI slave I2C master I2C slave SPI_MISO SPI_MOSI SPI_CSB SPI_CLK I2C_SDA I2C_CLK I2C_SDA I2C_CLK I2C_SDA I2C_CLK I2C_SDA I2C_C
PAGE 15
DA16200MOD Ultra Low Power Wi-Fi Module 5 5.1 Electrical Specification Absolute Maximum Ratings Table 3: Absolute Maximum Ratings Parameter Pins Min VBAT_3V3 35 VSS 3.9 V VDD_DIO1 34 VSS 3.9 V VDD_DIO2 15 VSS 3.9 V -40 +85 °C Operating temperature range (TA) 5.2 Max Units Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Pins VBAT_3V3 35 2.1 3.6 V VDD_DIO1 34 1.62 3.6 V VDD_DIO2 15 1.62 3.
PAGE 16
DA16200MOD Ultra Low Power Wi-Fi Module 5.3.2 DC Parameters, 3.3 V IO Table 6: DC Parameters, 3.3 V IO Parameter Symbol Condition Min Input Low Voltage VIL Guaranteed logic Low level Input High Voltage VIH Guaranteed logic High level Output Low Voltage VOL Output High Voltage Typ Max Units VSS 0.8 V 2.0 DVDD V DVDD=Min. VSS 0.4 V VOH DVDD=Min. 2.4 DVDD V Pull-up Resistor RPU VPAD=VIH, DIO=Min. 19.4 Pull-down Resistor RPD VPAD=VIL, DIO=Min. 16.0 kΩ Note 1 5.3.
PAGE 17
DA16200MOD Ultra Low Power Wi-Fi Module Table 10: DC Parameters for Digital Wake-up, 2.1 V VBAT & 1.8 V IO Parameter Symbol Condition Min Input Low Voltage VIL Guaranteed logic Low level Input High Voltage VIH Guaranteed logic High level Typ Max Units VSS 0.3 V 1.3 DVDD V (DVDD= 1.8V, VDD_DIO1, VDD_DIO2 Logic Level, DVDD should not be over VBAT) 5.4 5.4.1 Radio Characteristics WLAN Receiver Characteristics TA = +25 °C, VBAT = 3.
PAGE 18
DA16200MOD Ultra Low Power Wi-Fi Module Parameter Condition Min Typ Max 36 Mbps OFDM 14.5 17.0 18 48 Mbps OFDM 13 15.5 16.5 54 Mbps OFDM 12 14.5 15.5 MCS0 OFDM 15.5 18.0 19 MCS7 OFDM 12 14.5 15.5 Transmit center frequency accuracy 5.5 -25 Units +25 ppm Units Current Consumption TA = +25 °C, VBAT = 3.3 V, w/ CPU clock is 80 MHz. Table 13: Current Consumption in Active State Parameter Condition Min Typ Max 1 Mbps DSSS @ 19.0 dBm 260 280 320 6 Mbps OFDM @ 18.
PAGE 19
DA16200MOD Ultra Low Power Wi-Fi Module 5.6 Radiation Performance Figure 5: TIS 3D 5.7 Figure 6: TRP 3D ESD Ratings Table 15: ESD Performance Reliability Test Standards Test Conditions Result Human Body Model (HBM) ANSI/ESDA/JEDEC JS-001-2017 ± 2,000 V Pass Charge Device Mode (CDM) ANSI/ESDA/JEDEC JS-002-2018 ± 500 V Pass 5.8 Clock Electrical Characteristics DA16200MOD is including two clock sources. One is the 32.
PAGE 20
DA16200MOD Ultra Low Power Wi-Fi Module 6 Power Management DA16200MOD has an RTC block which provides power management and function control for low power operation. In normal operation, the RTC block is always powered on when RTC_PWR_KEY is enabled. 6.1 Power On Sequence The sequence after the initial switching from power-off to power-on is shown in Figure 7. The RTC_PWR_KEY of DA16200 is a pin that enables the RTC block.
PAGE 21
DA16200MOD Ultra Low Power Wi-Fi Module 6.2.2 Sleep Mode 2 Sleep mode 2 is an operational mode in which the RTC_PWR_KEY is set to high and the RTC block is running. Sleep mode 2 is activated by setting RTC registers for controlling the power management unit via a command from the CPU. To switch Sleep mode 2 back to Sleep mode 1, RTC_PWR_KEY should be set to low. Changing the state of the device from Sleep mode 2 to an ACTIVE state happens in one of two ways: 1.
PAGE 22
DA16200MOD Ultra Low Power Wi-Fi Module 7 Core System 7.1 ARM Cortex-M4F Processor The Cortex-M4F processor is a low-power processor that features low gate count, low interrupt latency, low-cost debug, and includes floating point arithmetic functionality. The processor is intended for deeply embedded applications that require fast interrupt response features.
PAGE 23
DA16200MOD Ultra Low Power Wi-Fi Module Pin Name Pin Number RTC_WAKE_UP 4 RTC_WAKE_UP2 14 Description This pin is an input pin for receiving an external event signal from an external device like a sensor. The RTC block detects an external event signal via this pin and wakes up DA16200 from Sleep mode 2 or Sleep mode 3. RTC block has a 36-bit real time counter. Its resolution is equal to one clock period of 32.768 kHz. The count value can be read via the register read command. 7.3.
PAGE 24
DA16200MOD Ultra Low Power Wi-Fi Module Table 19: I/O Power Domain 7.4 [25] DIO1 [26] DIO2 [27] FDIO GPIOA[11:4] GPIOC[8:6] F_CLK TCLK/TMS F_CSN UART0_RXD/UART0_TXD F_IO0 to F_IO3 Pulse Counter 7.4.1 Introduction The pulse counter is a module which counts the number of rising or falling edges of input signals. And this counter module can run even in Sleep mode. It includes one 32-bit up-counter. The input channel can be chosen by register setting among the 11 digital I/Os.
PAGE 25
DA16200MOD Ultra Low Power Wi-Fi Module 8 Peripherals This section describes the peripherals that are supported by the DA16200MOD. 8.1 QSPI: Master with XIP Feature QSPI master supports 4-line SPI communication with commercial flash memory devices and uses Motorola SPI-compatible interface among SPI communication modes. The highest communication speed is the same as the AMBA bus clock, and the speed is adjustable in integer multiples.
PAGE 26
DA16200MOD Ultra Low Power Wi-Fi Module AHB BusMatrix AHB Bus S I-Cache Controller XI P path M S0 AHB Bus Configuration QSPI Master with XIP feature External Serial NOR Flash S1 AHB Bus DMA M DMA AHB Bus Figure 9: QSPI Master Block Diagram Figure 10 shows the timing diagram for the QSPI master. TCLK.ON TDO.DLY TDI.SU TCSB.OF F QSPI_CSB QSPI_CLK QSPI_D[3:0] Figure 10: QSPI Master Timing Diagram (Mode 0) Datasheet CFR0011-120-00 Revision 3.
PAGE 27
DA16200MOD Ultra Low Power Wi-Fi Module Table 20 lists the timing parameters for the QSPI master. Table 20: QSPI Master Timing Parameters Parameter Symbol Min QSPI_CLK frequency FCLK 10 Typ QSPI_CLK clock duty Max Unit 120 MHz 50 % 1st CLK active rising transition time TCLK.ON 0.5 ×TCLK TCLK (Note 1) ns QSPI_CSB non-active rising transition time TCSB.OFF 0 TCLK ns QSPI_D[3:0] input setup time TDI.SU 6 QSPI_D[3:0] output delay time TDO.DLY Note 1 8.
PAGE 28
DA16200MOD Ultra Low Power Wi-Fi Module Table 22: SPI Master Timing Parameters Parameter Symbol Min QSPI_CLK frequency FCLK 5 Typ QSPI_CLK clock duty Max Unit 60 MHz 50 % 1st CLK active rising transition time TCLK.ON 0.5 × TCLK TCLK (Note 1) ns QSPI_CSB non-active rising transition time TCSB.OFF 0 TCLK ns QSPI_D[3:0] input setup time TDI.SU 6 QSPI_D[3:0] output delay time TDO.DLY Note 1 8.
PAGE 29
DA16200MOD Ultra Low Power Wi-Fi Module The 8-byte control type uses 4-byte address, 1-byte control, and 3-byte length. The 4-byte address displays the address of registers subject to internal access. The 1-byte control is for communication control and 3-byte length shows the length of data subject to continuous access in bytes. Hence, when the 8-byte control type is applied, the maximal length of data subject to continuous access is 16 MB.
PAGE 30
DA16200MOD Ultra Low Power Wi-Fi Module SPI_CSB TSCLKOFF TSCLKL TSCLKH TSCLKH TSCLKL TCSBOFF TSCLKON SPI_CLK (CPOL=0) SPI_CLK (CPOL=1) TMSU SPI_MOSI TSSU TMHD MSB LSB SPI_MISO LSB TTR Figure 15: SPI Slave Timing Diagram Table 26 lists the timing parameters for the SPI slave.
PAGE 31
DA16200MOD Ultra Low Power Wi-Fi Module Command Decoder Fn0 / Fn1 Decoder DAT Decoder APB bus Interface Response Generator CRC Generator REG. Control 2 port Memory DMA Controller Figure 16: SDIO Slave Block Diagram Table 27 shows the pin definition of the SDIO interface. The GPIOA4 and GPIOA5 pins are set to SDIO CMD and CLK by default. If SDIO initialization is performed and SDIO communication is enabled, SDIO data pin setting is performed automatically.
PAGE 32
DA16200MOD Ultra Low Power Wi-Fi Module Parameter Symbol SDIO_CMD output delay time TCO.DLY SDIO_D[3:0] input setup time TDI.SU SDIO_D[3:0] output delay time TDO.DLY Note 1 8.5 Min Typ Max Unit 11 (Note 1) ns 3 ns 11 (Note 1) ns SDIO signals can set previous output from half cycle. I2C Interface 8.5.1 I2C Master DA16200MOD includes an I2C master module. Three ranges of clock speed are supported: standard (100 kHz), fast (400 kHz), and high (1.0 MHz) speed mode.
PAGE 33
DA16200MOD Ultra Low Power Wi-Fi Module Fast Mode Parameter High Speed Mode Symbol SCL clock frequency Unit FSCLK Clock Duty (Note 1) Min Max Min Max 100 400 100 1000 (Note 2) kHz 40 60 40 60 % Hold time of START THD;STA 0.2 - 0.2 - μs Low period of the SCL clock TLOW 1.27 - 0.55 - μs High period of the SCL clock THIGH 1.23 - 0.45 - μs Setup time for START condition TSU;STA 1.1 - 0.
PAGE 34
DA16200MOD Ultra Low Power Wi-Fi Module Figure 19 shows the I2C slave timing diagram. TR ... SDA TR SCL TSU;DAT TVD;ACK cont. TLOW ... THD;STA THD;DAT THIGH S TBUF ... SDA cont. THD;STA ... SCL TSU;STO TSU;STA Sr P S Figure 19: I2C Slave Timing Diagram Table 32 lists the I2C slave timing parameters.
PAGE 35
DA16200MOD Ultra Low Power Wi-Fi Module 8.6 SD/SDeMMC The SD/eMMC host IP provides the function for DA16200MOD to access SD or eMMC cards. This SD/eMMC host IP only supports a 4-bit data bus and the maximum clock rate is 50 MHz. The maximum data rate is 25 MB/s (200 Mbps) under the 4-bit data bus and 50 MHz clock. SD/eMMC pin mux condition is defined in Table 33.
PAGE 36
DA16200MOD Ultra Low Power Wi-Fi Module Table 34 lists the timing parameters for the SD/eMMC master. Table 34: SD/eMMC Master Timing Parameters Parameter Symbol Min Typ Max Unit SD/eMMC_CLK frequency FSCLK - - 50 MHz SD/eMMC_CLK clock duty 50 SD/eMMC_CMD input setup time TCI.SU SD/eMMC_CMD output delay time TCO.DLY SD/eMMC_D[3:0] input setup time TDI.SU SD/eMMC_D[3:0] output delay time TDO.DLY 8.7 % 8 ns 3 ns 8 ns 8 ns I2S DA16200MOD provides an I2S interface.
PAGE 37
DA16200MOD Ultra Low Power Wi-Fi Module 8.7.1 Block Diagram I2S has the following features: ■ ■ ■ ■ ■ Master Clock Mode only I2S Data pin can work in either input mode or output mode Clock source can be "internal 480 MHz/N" (currently using 24 MHz) or "external clock source" Max Sampling Rate: 48 KHz Mono/Stereo Mode Figure 22: I2S Block Diagram 8.7.2 I2S Clock Scheme The I2S uses a 24 MHz clock as default from the RF reference clock (40 MHz), so it can support 46.875 KHz of sampling rate.
PAGE 38
DA16200MOD Ultra Low Power Wi-Fi Module Table 36: I2S Clock Selection Guide Parameter Units LRCK Fs 8 12 16 24 32 44.1 46.875 48 KHz BCLK 64Fs 0.512 0.768 1.024 1.536 2.048 2.8224 3 3.072 MHz MCLK 512Fs 4.096 6.144 8.192 12.288 16.384 22.5792 24 24.576 MHz Clk Div2 N (=1,2,3…) 6 4 3 2 2 1 1 1 24.576 24.576 24.576 24.576 32.768 22.5792 24 (Internal PLL) 24.576 I2S_CLK NOTE To confirm the exact LRCK operation, drive the Clock source at I2S_CLK. 8.7.
PAGE 39
DA16200MOD Ultra Low Power Wi-Fi Module T2 fBCLK T3 I2S_BCLK T4 I2S_SDO (falling edge) T5 I2S_SDO (rising edge) Figure 27: I2S Transmit Timing Diagram T4 T2 T3 fBCLK I2S_BCLK T5 I2S_SDO Figure 28: I2S Receive Timing Diagram Table 37: I2S Transmit Timing Parameters Description Timing Min I2S_BCLK frequency fBCLK High period of the BCLK clock Typ Max Unit - 3.
PAGE 40
DA16200MOD Ultra Low Power Wi-Fi Module VI_N[1] ADC 12b Max : 1Ms Switch VI_N[3] CH_SEL ADC Controller SWITCH VI_N[2] Ready VI_N[4] Counter 16-bit Figure 29: ADC Control Block Diagram 8.8.2 Timing Diagram The input is digitized at a maximum of 1.0 Msps throughput rate. And the maximum input clock rate is 15 MHz. Figure 30 shows the conversion timing, and Table 39 describes DC specifications.
PAGE 41
DA16200MOD Ultra Low Power Wi-Fi Module 8.8.4 Sensor Wake-up DA16200MOD provides an external sensor wake-up function using the analog input signal through this Aux ADC. Even in Sleep modes, it detects the change of external analog signal, wakes up from a Sleep mode, and converts DA16200MOD into a normal operation. This function can be used in up to four channels. Also, when multiple external sensors are used, it detects analog signals while changing the channel automatically.
PAGE 42
DA16200MOD Ultra Low Power Wi-Fi Module Antenna1 RF RF Switch Switch FC9050 DA16200MOD-AAE Antenna2 ANT GPIO 2 Figure 31: Antenna Switching Internal Block Diagram If the Antenna Switching Diversity function is enabled, the function is automatically done by PHY hardware block.
PAGE 43
DA16200MOD Ultra Low Power Wi-Fi Module Figure 32: Antenna Switching Timing Diagram For reference, this antenna switching diversity is different from MRC. (Maximum Ratio Combining) 8.
PAGE 44
DA16200MOD Ultra Low Power Wi-Fi Module Figure 33: DA16200 UART Block Diagram 8.10.1 RS-232 As the serial communication between the UART and the selected device is asynchronous, additional bits (start and stop) are inserted to the data line to indicate the beginning and end. By these bits, two devices can be synchronized. This structure of serial data accompanied by start and stop bits is referred to as a character, as shown in Figure 34.
PAGE 45
DA16200MOD Ultra Low Power Wi-Fi Module An additional parity bit may be added to the serial character. This bit appears between the last data bit and the stop bit(s) in the character structure. It provides the UART with the ability to perform simple error checking on the received data. The UART Line Control Register is used to control the serial character characteristics. The individual bits of the data word are sent after the start bit, starting with the least significant bit (LSB).
PAGE 46
DA16200MOD Ultra Low Power Wi-Fi Module Then, generated baud rate divider is 5 + 27/64 = 5.422. Finally, generated baud rate becomes (8 x 107) / (16 x 5.422) = 922169. And the error between required baud rate and generated baud rate is (922169 – 921600) / 921600 x100 = 0.062%. 8.10.4 Hardware Flow Control Hardware flow control feature is fully selectable, and serial data flow is controlled by using nUARTRTS output and nUARTCTS input signals.
PAGE 47
DA16200MOD Ultra Low Power Wi-Fi Module Table 42: UART Interrupt Signals Signal Name Description UARTMSINTR UART Modem Status Interrupt UARTRXINTR UART Receive FIFO Interrupt UARTTXINTR UART Transmit FIFO Interrupt UARTRTINTR UART Receive Timeout Interrupt UARTEINTR UART Error Interrupt UARTINTR UART Interrupt. Five Interrupt signals are combined by OR function 8.10.
PAGE 48
DA16200MOD Ultra Low Power Wi-Fi Module 8.11 PWM Pulse Width Modulation (PWM) is a modulation technique used to encode a message into a pulse signal. The blocks are designed to adjust output pulse duration by the CPU bus clock (HCLK). Figure 38 shows the structure of the PWM block.
PAGE 49
DA16200MOD Ultra Low Power Wi-Fi Module Table 45: PWM Timing Diagram Description Time Description a Bus Clock Period × (nCycle High + 1) b Bus Clock Period × (nCycle Period + 1) 8.12 Debug Interface DA16200MOD supports both IEEE Standard 1149.1 JTAG (5-wire) and the low-pin-count ARM SWD (2-wire, TCLK/TMS) debug interfaces. The SWD protocol can handle the same debug features as the JTAG.
PAGE 50
DA16200MOD Ultra Low Power Wi-Fi Module Table 47 shows the pin definition of the JTAG interface. Table 47: JTAG Pin Configuration Pin Name Pin Number I/O Function Name TMS 7 I/O Data TCLK 8 I Clock GPIOC8 9 I TDI: Data Input GPIOC7 10 O TDO: Data Output GPIOC6 11 I nTRST: Reset 8.13 Bluetooth Coexistence DA16200MOD provides the Bluetooth coexistence function to be properly aligned with external devices activated at 2.4 GHz. 8.13.
PAGE 51
DA16200MOD Ultra Low Power Wi-Fi Module ○ If it is used and DA16200’s iBtAct = Active while iBTPri = Non-Active, DA16200 may ignore iBtAct Datasheet CFR0011-120-00 Revision 3.
PAGE 52
DA16200MOD Ultra Low Power Wi-Fi Module 9 Applications Schematic NC NC 7 JTAG interface 8 9 GPIO I nterface 10 11 12 13 RTC_SENSOR GPIO A1 NC GPIO A2 JTAG_TMS GPIO A4 GPIOC8 GPIO A5 GPIO C7 GPIOA6 GPIO C6 GPIO A7 UART0_TXD GPIO A8 UART0_RXD GPIO A9 14 If the RTC_WAKE_UP2 function is not uesd, it can be connected to the GND GPIO A3 DA16200MOD JTAG_TCLK VDD_DIO2 RTC_WAKE_UP2 UART interface for debugging GPIO A0 15 16 17 18 19 20 21 22 1uF 10uF 35 VBAT_3V3 34 VDD_DI
PAGE 53
DA16200MOD Ultra Low Power Wi-Fi Module 10 Package Information 10.1 Dimension: DA16200MOD-AAC Unit: mm Tolerance: 13.8(±0.2) x 22.1(±0.2) x 3.3(±0.1) Figure 43: AAC Module Dimension 10.2 Dimension: DA16200MOD-AAE Unit: mm Tolerance: 13.8(±0.2) x 22.1(±0.2) x 3.3(±0.1) Figure 44: AAE Module Dimension Datasheet CFR0011-120-00 Revision 3.
PAGE 54
DA16200MOD Ultra Low Power Wi-Fi Module 10.3 PCB Land Pattern Unit: mm Figure 45: PCB Land Pattern (Top View) Figure 46: PCB Land Pattern (Bottom View) Ant GND is only needed on the bottom of the PCB. GND must be removed for all layers including the inner layer except the bottom. See Figure 47 for detail. Datasheet CFR0011-120-00 Revision 3.
PAGE 55
DA16200MOD Ultra Low Power Wi-Fi Module 10.4 4-Layer PCB Example Figure 47: 4-Layer PCB Example Datasheet CFR0011-120-00 Revision 3.
PAGE 56
DA16200MOD Ultra Low Power Wi-Fi Module 10.5 Soldering Information 10.5.1 Condition for Reflow Soldering Figure 48 shows the typical process flow for mounting surface mount packages to PCB. The reflow profile depends on the solder paste being used and the recommendations from the paste manufacture should be followed to determine the proper reflow profile. Figure 49 shows a typical reflow profile when a no-clean paste is used. Oven time above liquidus (260 °C for lead-free solder) is 20 to 40 seconds.
PAGE 57
DA16200MOD Ultra Low Power Wi-Fi Module Table 49: Typical Reflow Profile (Lead Free): J-STD-020C Profile Feature Lead Free SMD Average ramp up rate (Tsmax to Tp) 3 °C/s Max.
PAGE 58
DA16200MOD Ultra Low Power Wi-Fi Module 11 Ordering Information The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult Dialog Semiconductor’s Website or your local sales representative. Table 50: Ordering Information (Production) Part Number Pins Size (mm) Shipment Form Pack Quantity DA16200MOD-AAC4WA32 37 13.8 x 22.1 x 3.3 Reel MOQ: 500 pcs DA16200MOD-AAE4WA32 37 13.8 x 22.1 x 3.
PAGE 59
DA16200MOD Ultra Low Power Wi-Fi Module Revision History Revision Date Description ● Editorial ● Removed BOR part ● Added Note for Power on Sequence in the Section 6.1, Updated Figure 7 3.1 and Table 16 03-Fab-21 ● Section 8.7.3 Fixed typo ● Added Section 8.7.1 and 8.7.2 ● Updated Applications Schematic 3.0 23-Jul-20 ● Sync with SoC datasheet v3.1 ● Modified Chapter 3 description to Network subsystem layer.
PAGE 60
DA16200MOD Ultra Low Power Wi-Fi Module Status Definitions Revision Datasheet Status Product Status Definition 1. Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2. Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production.