Datasheet

3 Pin Definitions
Table 2 – cont’d from previous page
Name No. Type
1
Function
IO7 6 I/O/T GPIO7, FSPID, MTDO
IO8 7 I/O/T GPIO8
IO9 8 I/O/T GPIO9
GND 9,19 P Ground
IO10 10 I/O/T GPIO10, FSPICS0
RXD 11 I/O/T GPIO20, U0RXD
TXD 12 I/O/T GPIO21, U0TXD
IO18 13 I/O/T GPIO18, USB_D-
IO19 14 I/O/T GPIO19, USB_D+
IO3 15 I/O/T GPIO3, ADC1_CH3
IO2 16 I/O/T GPIO2, ADC1_CH2, FSPIQ
IO1 17 I/O/T GPIO1, ADC1_CH1, XTAL_32K_N
IO0 18 I/O/T GPIO0, ADC1_CH0, XTAL_32K_P
1
P: power supply; I: input; O: output; T: high impedance.
3.3 Strapping Pins
Note:
The content below is excerpted from Section Strapping Pins in ESP32-C3 Family Datasheet . For the strapping pin
mapping between the chip and modules, please refer to Chapter 5 Module Schematics.
ESP32-C3 family has four strapping pins:
• GPIO2
• GPIO8
• GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference Manual.
During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.
Types of system reset include:
• power-on-reset
• RTC watchdog reset
• brownout reset
• analog super watchdog reset
• crystal clock glitch detection reset
By default, GPIO9 is connected to the internal pull-up resistor. If GPIO9 is not connected or connected to an
external high-impedance circuit, the latched bit value will be ”1”
Espressif Systems 12
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ESP32-C3-WROOM-02 & WROOM-02U Datasheet v0.7