Datasheet

6. Peripheral Schematics
6. Peripheral Schematics
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
X1: ESR = Max. 70 KΩ
NC: No component.
EN
IO0
IO12
IO13
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO42
IO41
IO37
IO36
IO38
IO40
IO39
IO14
IO15
IO16
IO17
IO19
IO20
IO21
IO26
IO46
RXD0
TXD0
IO45
EN
IO35
IO34
IO33
TMS
TDI
TDO
TCK
IO0
USB_D+
USB_D-
IO18
GND
GND GND
VDD33
GND GND
GND
GND
VDD33
GND
GND
GND
GND GND
VDD33
GND
C2
TBD
R3 0(NC)
SW1
C3
0.1uF
JP3
USB OTG
1
1
2
2
C6
20pF(NC)
C7 12pF(NC)
U1
ESP32-S2-WROOM/ESP32-S2-WROOM-I
GND
1
3V3
2
IO0
3
IO1
4
IO2
5
IO3
6
IO4
7
IO5
8
IO6
9
IO7
10
IO8
11
IO9
12
IO10
13
IO11
14
GND
42
IO45
39
RXD0
38
TXD0
37
IO42
36
IO41
35
IO40
34
IO39
33
IO38
32
IO37
31
IO36
30
IO35
29
IO34
28
IO33
27
IO14
17
IO15
18
IO16
19
IO17
20
IO18
21
IO19
22
IO20
23
IO21
24
IO26
25
GND
26
EPAD
43
IO12
15
IO13
16
EN
41
IO46
40
R4 0
R7 0
X1
32.768KHz(NC)
12
R2 NC
R1 TBD
JP4
Boot Option
1
1
2
2
C5
20pF(NC)
JP1
UART
1
1
2
2
3
3
4
4
C1
22uF
C4 12pF(NC)
C8 0.1uF
R6 0
R5 0(NC)
R8 10K
JP2
JTAG
1
1
2
2
3
3
4
4
Figure 6: Peripheral Schematics
Note:
Soldering the EPAD to the ground of the base board is not a must, though doing so can get optimized thermal
performance. If users do want to solder it, they need to ensure that the correct quantity of soldering paste is applied.
To ensure the power supply to the ESP32-S2 chip during power-up, it is advised to add an RC delay circuit at the
EN pin. The recommended setting for the RC delay circuit is usually R = 10 k and C = 0.1 µF. However, specific
parameters should be adjusted based on the power-up timing of the module and the power-up and reset sequence
timing of the chip. For ESP32-S2’s power-up and reset sequence timing diagram, please refer to Section Power
Scheme in ESP32-S2 Datasheet.
GPIO18 works as U1RXD and is in an uncertain state when the chip is powered on, which may affect the chip’s
entry into download boot mode. To solve this issue, add an external pull-up resistor.
Espressif Systems 20
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ESP32-S2-WROOM & ESP32-S2-WROOM-I Datasheet V1.1