Datasheet
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Avoid VREF pins due to their slow IO times.
UDCLK has to be a CTL pin.
DATA[0..7] have to be from GPIF[0..15]
FPGA "LEFT" BANK
Mini Expansion Header
FX3_UART_RX
FX3_UART_TX
LED1 LED2
LED1
LED2
MINI_EXP_1
MINI_EXP_1
MINI_EXP_2
MINI_EXP_2
LED3
LED3
VCCIO_L_C4
VD3P3 VD3P3
VD3P3
VD3P3
GPIF6
GPIF1
GPIF0
GPIF3
GPIF8
GPIF5
GPIF10
GPIF12
GPIF11
GPIF13
GPIF14
FX3_CTL0
FX3_CTL1
FX3_CTL6
FX3_CTL2
FX3_CTL11
FX3_CTL10
GPIF17
GPIF20
GPIF16
GPIF19
GPIF21
GPIF22
GPIF25
GPIF27
GPIF29
FX3_CTL5
FX3_CTL3
FX3_PCLK
FX3_CTL12
FX3_CTL8
GPIF28
GPIF23
GPIF24
GPIF30
GPIF31
FX3_CTL9 C4_DCLK
GPIF15
GPIF26FX3_CTL7
GPIF7
FX3_CTL4
GPIF9
GPIF4
GPIF2
GPIF18
DAC_SDO
DAC_SDI
C4_CLK
DAC_SCLK
DAC_CSB
FX3_UART_TX
nFX3_UART_CS
FX3_UART_RX
C4_CONFDONE
C4_NCONFIG
C4_NSTATUS
FX3_GPIO50
FX3_GPIO51
FX3_GPIO52
SI_SCL
SI_SDA
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
Nuand
B
3 14Saturday, March 30, 2013
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
Nuand
B
3 14Saturday, March 30, 2013
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
Nuand
B
3 14Saturday, March 30, 2013
C242
0.01uF
C242
0.01uF
C252
0.01uF
C252
0.01uF
J64
HEADER_1x3_100mil
J64
HEADER_1x3_100mil
1
2
3
R287
820
R287
820
BANK 3
EP4CE15A115F484
U43F
BANK 3
EP4CE15A115F484
U43F
B3_IO_U9
U9
B3_IO_U10
U10
B3_IO_U11_VREF
U11
B3_IO_V5
V5
B3_IO_V8
V8
B3_IO_V9_VREF
V9
B3_IO_V10
V10
B3_IO_V11
V11
B3_IO_W6
W6
B3_IO_W7
W7
B3_IO_W8
W8
B3_IO_W10
W10
B3_IO_Y3
Y3
B3_IO_Y4_VREF
Y4
B3_IO_Y6
Y6
B3_IO_Y7
Y7
B3_IO_Y8
Y8
B3_IO_Y10
Y10
B3_IO_AA3
AA3
B3_IO_AA4
AA4
B3_IO_AA5
AA5
B3_IO_AA7
AA7
B3_IO_AA8
AA8
B3_IO_AA9
AA9
B3_IO_AA10
AA10
B3_CLK15
AA11
B3_IO_AB3
AB3
B3_IO_AB4_VREF
AB4
B3_IO_AB5
AB5
B3_IO_AB7
AB7
B3_IO_AB8
AB8
B3_IO_AB9
AB9
B3_IO_AB10
AB10
B3_CLK14
AB11
R278
820
R278
820
D13
LTST-C190KGKT
D13
LTST-C190KGKT
BANK 1
EP4CE15A115F484
U43D
BANK 1
EP4CE15A115F484
U43D
B1_IO_B1
B1
B1_IO_B2
B2
B1_IO_C1
C1
B1_IO_C2
C2
B1_IO_D1_DATA1_ASDO
D1
B1_IO_D2
D2
B1_IO_E1
E1
B1_IO_E2_FLASH_nCE_nCSO
E2
B1_IO_E3
E3
B1_IO_E4_NRESET
E4
B1_IO_F1
F1
B1_IO_F2
F2
B1_CLK1
G1
B1_IO_G3
G3
B1_IO_G5_VREF
G5
B1_IO_H1
H1
B1_IO_H2
H2
B1_IO_H5_VREF
H5
B1_IO_H6
H6
B1_IO_H7_VREF
H7
B1_IO_J1
J1
B1_IO_J2
J2
B1_IO_J3_VREF
J3
B1_IO_J4
J4
B1_IO_J6
J6
B1_IO_K1_DATA0
K1
R286
820
R286
820
BANK 8
EP4CE15A115F484
U43K
BANK 8
EP4CE15A115F484
U43K
B8_IO_A3_DATA10
A3
B8_IO_A4
A4
B8_IO_A5_DATA5
A5
B8_IO_A6_PADD19
A6
B8_IO_A7_PADD18
A7
B8_IO_A8_DATA2
A8
B8_IO_A9_PADD16
A9
B8_IO_A10
A10
B8_CLK10
A11
B8_IO_B3_DATA11
B3
B8_IO_B4_DATA8
B4
B8_IO_B5_VREF
B5
B8_IO_B6_DATA15
B6
B8_IO_B7_DATA4
B7
B8_IO_B8_DATA3
B8
B8_IO_B9_PADD17
B9
B8_IO_B10_PADD15
B10
B8_CLK11
B11
B8_IO_C3
C3
B8_IO_C4_DATA12
C4
B8_IO_C6_DATA7
C6
B8_IO_C7_DATA13
C7
B8_IO_C8_DATA14
C8
B8_IO_C10_VREF
C10
B8_IO_D6_VREF
D6
B8_IO_D10
D10
B8_IO_E5
E5
B8_IO_E6
E6
B8_IO_E7
E7
B8_IO_E9_VREF
E9
B8_IO_F7
F7
B8_IO_F8_DATA9
F8
B8_IO_F9
F9
B8_IO_F10_DATA6
F10
D11
LTST-C190KGKT
D11
LTST-C190KGKT
D12
LTST-C190KGKT
D12
LTST-C190KGKT
BANK 2
EP4CE15A115F484
U43E
BANK 2
EP4CE15A115F484
U43E
B2_IO_L6
L6
B2_IO_M1
M1
B2_IO_M2
M2
B2_IO_M3
M3
B2_IO_M4
M4
B2_IO_M5_VREF
M5
B2_IO_M6
M6
B2_IO_N1
N1
B2_IO_N2
N2
B2_IO_N5
N5
B2_IO_N6
N6
B2_IO_P1
P1
B2_IO_P2
P2
B2_IO_P3
P3
B2_IO_P4
P4
B2_IO_P5
P5
B2_IO_R1
R1
B2_IO_R2
R2
B2_IO_R5_VREF
R5
B2_CLK3
T1
B2_CLK2
T2
B2_IO_T3_VREF
T3
B2_IO_T4
T4
B2_IO_T5
T5
B2_IO_U1
U1
B2_IO_U2
U2
B2_IO_V1
V1
B2_IO_V2
V2
B2_IO_V3
V3
B2_IO_V4
V4
B2_IO_W1
W1
B2_IO_W2
W2
B2_IO_Y1
Y1
B2_IO_Y2
Y2
B2_IO_AA1
AA1
J71
PWR_HDR6
J71
PWR_HDR6
1
2
3 4
6
5