5 4 3 2 1 bladerRF - USB 3.
5 4 3 2 1 FPGA CONFIGURATION D VCCIO_L_C4 D Config is on BANK 1 aka VCCIO_L_C4 R255 10K VCCIO_L_C4 C4_CONFDONE C4_CONFDONE R256 10K U43C CONF_DONE NSTATUS NCONFIG NCE M18 K6 K5 L3 C4_NSTATUS C4_NCONFIG C4_NSTATUS C4_NCONFIG VCCIO_L_C4 DCLK C TMS TCK L1 L2 TDO TDI L4 L5 TMS TCK TDO TDI MSEL0 MSEL1 MSEL2 MSEL3 K2 M17 L18 L17 K20 C4_DCLK MSEL0 MSEL1 MSEL2 MSEL3 VCCIO_L_C4 R259 R273 10K C 10K EP4CE15A115F484 MSEL[3..
5 4 3 Avoid VREF pins due to their slow IO times. UDCLK has to be a CTL pin. DATA[0..7] have to be from GPIF[0..
3 2 FPGA "RIGHT" BANK Expansion Header U43I U43G BANK 4 R16 T15 T16 U12 U14 V12 V13 V14 V15 V16 W13 W14 W15 W17 Y13 Y17 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 LMS_RESET LMS_RXEN LMS_SCLK C TX_V2 LMS_SDIO LMS_SDO LMS_TXEN LMS_SEN RX_V2 RX_V1 B4_IO_R16 B4_IO_T15 B4_IO_T16 B4_IO_U12 B4_IO_U14 B4_IO_V12_VREF B4_IO_V13 B4_IO_V14 B4_IO_V15 B4_IO_V16_VREF B4_IO_W13 B4_IO_W14_VREF B4_IO_W15 B4_IO_W17 B4_IO_Y13 B4_IO_Y17 B4_CLK13 B4_IO_AA13 B4_IO_AA14 B4_IO_
4 3 VCCIO_L_C4 defines the "left" banks of the C4 VCCIO_R_C4 defines the "right" banks of the C4 The left side goes to the FX3, and the right side goes to the LMS. VCCIO_L_C4 2 1 FPGA POWER VCCINT @1.2V, MAX 3.1A VCCA2P5 @ 2.5, MAX 0.1A VCCIO @1.8V MAX 0.
5 4 3 2 FX3 GPIF + BOOT U2A P - PORT 1 U2C S1 - PORT SEC 3/7 SEC 1/7 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 C DQ14 VIO1 DQ15 PCLK CTL0 CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 CTL7 CTL8 B CTL9 CTL10 CTL11 CTL12 PMODE0 PMODE1 PMODE2 INT_N_CTL15 GPIF2 G10 GPIF3 G9 GPIF4 F8 GPIF5 H10 GPIF6 H9 GPIF7 J10 GPIF8 J9 GPIF9 K11 GPIF10 L10 GPIF11 K10 GPIF12 K9 GPIF13 J8 GPIF14 G8 GPIF15 J6 FX3_PCLK K8 FX3_CTL0 K7 FX3_CTL1 J7 FX3_CTL2 H7 FX3_CTL3 G7 FX3_CTL4 G6
5 4 3 2 1 FX3 DEBUG + CLOCK SEL U2F MISC SEC 6/7 D I2C-GPIO58_SCL I2C-GPIO59_SDA VIO5 I2C-GPIO60_CHARGER-DETECT TCK TDI TDO TMS TRST_N D9 FX3_I2C_SCL D10 FX3_I2C_SDA DEBUG TPs Debug LED D FX3_I2C_SCL FSLC[2..0] D11 CHARGER_DETECT F6 TCK E7 TDI C10 TDO E8 TMS CVDDQ B11 D10 LTST-C190KGKT R1 10K TP6 TRST_N CVDDQ R2 10K CHARGER_DETECT FSLC2 FSLC1 FSLC0 FX3 C C R3 10K FX3 JTAG FX3 datasheet pg 8: 38.
5 4 3 2 1 USB CONNECTIONS USB3.0 D MICRO TYPE B D U2D BLM21PG221SN1D SEC 4/7 VBUS/ VBAT L2 J48 U - PORT VBUS OTG_ID E11 VBUS USB3_VBUS D- C9 OTG_ID A4 A3 SS_RX_P SS_RX_M ID D+ SSRXP SSRXM VBUS SSTXP SSTXM DP DM A5 A6 C43 0.1uF SS_TX_P GND1 C46 0.1uF SS_TX_M MICRO_SSTX- SS_DP SS_DM MICRO_SSTX+ A9 A10 GND2 VBUS/ VBAT MICRO_SSRX- C NC R_USB2 R_USB3 A11 MICRO_SSRX+ C8 6.
5 4 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 SEC 7/7 VIO5 A2 B5 AVDD VIO3 U3RXVDDQ CVDDQ U3TXVDDQ VIO4 VIO1_1 VIO1_2 G1 L1 E2 L6 D8 G11 L11 K4 L3 K3 L2 A8 C VDD_FX FB7 MPZ2012S601A E10 C367 22uF C78 C79 C80 C81 C82 C83 C84 C85 C106 C107 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF D C11 VIO2_FX VIO2 A7 U3TX_VDDQ V1P2 VIO5_FX AVDD_FX U3RX_VDDQ VBAT 1 VDD POWER H1 C3 L7 E9 F11 L5 J11 B10 D 2 FX3 POWER VDD+AVDD 1.2V@200mA U3VDDQ 1.
5 4 Analog 1.8V 3 LMS DIGITAL Digital 1.8V Analog 40mA 2 Digital 45.51mA VD1P8 VA1P8 L19 MMZ0603S601C L16 MMZ0603S601C R290 DNP D L20 MMZ0603S601C RAVDD18 RXVCCPLL18 C199 1uF C196 0.1uF LMS_RXEN R260 TXVDDVCO18 R289 DNP 1 PLLCLK is Vref'd by PVDDSPI33 Digital 1.8V U1B 71 C231 LMS_CLK 0.
5 4 3 2 1 LMS ANALOG + RF U63 1 V3P3_TX_LMS 2 D 3 GND J1 J2 V2 AS211-334 C319 20pF C225 U1D 48 50 DNP U1C C320 20pF C313 3.6pF C314 3.6pF C R264 820 OEXLNA1P IEXMIX1P IEXMIX1N OEXLNA1N RXIN1EP RXIN1EN J61 6 1 5 2 4 3 116 115 113 114 RXOUTIP RXOUTIN RXOUTQP RXOUTQN 6 SD L36 91 92 94 95 97 99 C312 3.6pF 36nH L34 C315 3.6pF 36nH L35 1.5GHz - 3.8GHz AS211-334 V3P3_TX_LMS 3 PWR_HDR6 2 C240 1 RXIN1P RXIN1N 96 98 0.1uF 1uF 1.
5 4 3 2 1 CLOCKS V3P58 L47 MMZ1005S601C VCCIO_R_C4 D D U55 1 3 2 VIN SHDN GND L51 MMZ1005S601C L46 OUT 5 VCCIO_R_C4_CLK MMZ1005S601C BYPASS 4 TC1014-3.0VCT713 D1 LTST-C190KGKT C365 1uF C219 0.1uF V1P8_CLK C218 0.1uF L55 MMZ1005S601C A1 B1 C1 D1 C228 1uF VBATT VLDO MCLK_IN GND C220 1uF CLK_OUT1 CLK_REQ1 CLK_REQ2 CLK_OUT2 A2 B2 C2 D2 FX3_CLK R277 1.2K R284 200 U68 1 2 3 CDC3RL02 IN1 IN2 IN3 VDD1 VDD2 U67 7 24 Digital 10mA C362 470pF Analog 2mA SI_SCL SI_SDA C229 0.
5 4 3 2 1 POWER DISTRIBUTION The idea is to drop to 1.2V and 3.58V with SMPS. Then drop to 3.3, 2.5, 1.8 from the 3.58V SMPS. Analog 3.3V 280mA / 500mA VDO @ 500mA 100mV V3P3_TX_LMS FB11 1.2V (min:200mA, typ:800mA) / 3100mA / 90% eff D MPZ2012S601A 16 4 C354 22uF 2mOhm 5 C353 0.1uF R303 4.32K EN FB AVIN PGOOD RT COMP NC LM20145 9 8 SS/TRK 2 R301 5.9K GND GND 3 6 C355 2.2uF D Analog 3.
5 4 3 2 1 POWER SELECTION + DEBUG D D Jumpered power selection DC barrel vs USB3 bus J49 VDC 2 1 3 J70 1 6 2 5 3 4 V5P0 RAPC712X Manufacturer = Switchcraft Inc. PART_NUMBER = RAPC712X VBUS_IN C121 PWR_HDR6 + 100uF_10V C123 + C122 100uF_10V + + C124 330uF_10V 330uF_10V C C B B Scatter these testpoints throughout the design.