Data Sheet

DocID023111 Rev 3 33/38
H3LIS331DL Register description
38
Configuration register for interrupt 2 source.
7.18 INT2_SRC (35h)
Interrupt 2 source register. Read-only register.
Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2
pin) and allows the refreshment of data in the INT2_SRC register if the latched option is
chosen.
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Table 48. Interrupt mode configuration
AOI Interrupt mode
0 OR combination of interrupt events
1 AND combination of interrupt events
Table 47. INT2_CFG description (continued)
Table 49. INT2_SRC register
0 IA ZHZLYHYLXHXL
Table 50. INT2_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X Low. Default value: 0
(0: no interrupt, 1: X low event has occurred)