Data Sheet

DocID023111 Rev 3 31/38
H3LIS331DL Register description
38
Configuration register for interrupt 1 source.
7.14 INT1_SRC (31h)
Interrupt 1 source register. Read-only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refreshment of data in the INT1_SRC register if the latched option is
chosen.
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Table 39. Interrupt 1 source configurations
AOI Interrupt mode
0 OR combination of interrupt events
1 AND combination of interrupt events
Table 38. INT1_CFG description (continued)
Table 40. INT1_SRC register
0 IA ZHZLYHYLXHXL
Table 41. INT1_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)