Data Sheet

DocID023111 Rev 3 27/38

H3LIS331DL Register description

7.4 CTRL_REG3 [interrupt CTRL register] (22h)

7.5 CTRL_REG4 (23h)

Table 25. CTRL_REG3 register

IHL PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0

Table 26. CTRL_REG3 description

IHL

Interrupt active high, low. Default value: 0

(0: active high; 1: active low)

PP_OD

Push-pull/open drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

LIR2

Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by

reading INT2_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I2_CFG1,

I2_CFG0

Data signal on INT 2 pad control bits. Default value: 00.

(see Table 27)

LIR1

Latch interrupt request on the INT1_SRC register, with the INT1_SRC register

cleared by reading the INT1_SRC register. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I1_CFG1,

I1_CFG0

Data signal on INT 1 pad control bits. Default value: 00.

(see Table 27)

Table 27. Data signal on INT 1 and INT 2 pad

I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pad

0 0 Interrupt 1 (2) source

0 1 Interrupt 1 source OR interrupt 2 source

1 0 Data ready

1 1 Boot running

Table 28. CTRL_REG4 register

BDU BLE FS1 FS0 0 0 0 SIM