Data Sheet

DocID023111 Rev 3 11/38
H3LIS331DL Mechanical and electrical specifications
38
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3. SPI slave timing diagram
(2)
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.
Table 5. SPI slave timing values
Symbol Parameter
Value
(1)
Unit
Min. Max.
t
c(SPC)
SPI clock cycle 100 ns
f
c(SPC)
SPI clock frequency 10 MHz
t
su(CS)
CS setup time 6
ns
t
h(CS)
CS hold time 8
t
su(SI)
SDI input setup time 5
t
h(SI)
SDI input hold time 15
t
v(SO)
SDO valid output time 50
t
h(SO)
SDO output hold time 9
t
dis(SO)
SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.