Data Sheet

Page 98
RFM95/96/97/98(W)
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WIRELESS & SENSING PRELIMINARY DATASHEET
Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description
7 ModeReady r -
Set when the operation mode requested in Mode, is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- Rx: RSSI sampling starts
- Tx: PA ramp-up completed
Cleared when changing the operating mode.
6 RxReady r -
Set in Rx mode, after RSSI, AGC and AFC.
Cleared when leaving Rx.
5 TxReady r -
Set in Tx mode, after PA ramp-up.
Cleared when leaving Tx.
4 PllLock r -
Set (in FS, Rx or Tx) when the PLL is locked.
Cleared when it is not.
3 Rssi rwc -
Set in Rx when the RssiValue exceeds RssiThreshold.
Cleared when leaving Rx or setting this bit to 1.
2
Timeout r -
Set when a timeout occurs
Cleared when leaving Rx or FIFO is emptied.
1 PreambleDetect rwc -
Set when the Preamble Detector has found valid Preamble.
bit clear when set to 1
RegIrqFlags1
(0x3e)
0 SyncAddressMatch rwc -
Set when Sync and Address (if enabled) are detected.
Cleared when leaving Rx or FIFO is emptied.
This bit is read only in Packet mode, rwc in Continuous mode
7 FifoFull r - Set when FIFO is full (i.e. contains 66 bytes), else cleared.
6 FifoEmpty r -
Set when FIFO is empty, and cleared when there is at least 1 byte
in the FIFO.
5 FifoLevel r -
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
4 FifoOverrun rwc -
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The FIFO then
becomes immediately available for the next transmission /
reception.
3 PacketSent r -
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx
2 PayloadReady r -
Set in Rx when the payload is ready (i.e. last byte received and
CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared
when FIFO is empty.
1 CrcOk r -
Set in Rx when the CRC of the payload is Ok. Cleared when FIFO
is empty.
RegIrqFlags2
(0x3f)
0 LowBat rwc -
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set to 1 by the user.
IO control registers