Data Sheet

Page 85
RFM95/96/97/98(W)
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WIRELESS & SENSING PRELIMINARY DATASHEET
Register Name Description
Address
FSK/OOK Mode
LoRa
TM
Mode
Reset
(POR)
Default
(FSK)
FSK Mode
LoRa
TM
Mode
0x1D RegFeiMsb RegNbRxBytes 0x00 Number of received bytes
0x1E RegFeiLsb RegRxHeaderInfo 0x00
Value of the calculated
frequency error
Info from last header
0x1F RegPreambleDe-
tect
RegRx-
HeaderCntValue
0x40
0xAA
Settings of the Preamble
Detector
Number of valid headers
received
0x20 RegRxTimeout1 RegRxPacketCnt-
Value
0x00
Timeout Rx request and RSSI
Number of valid packets
received
0x21 RegRxTimeout2 RegModemStat 0x00
Timeout RSSI and Pay-
loadReady
Live LoRa
TM
modem sta-
tus
0x22 RegRxTimeout3 RegPktSnrValue 0x00 Timeout RSSI and SyncAd-
dress
Espimation of last packet
SNR
0x23 RegRxDelay RegRssiValue 0x00 Delay between Rx cycles Current RSSI
0x24 RegOsc RegPktRssiValue 0x05
0x07
RC Oscillators Settings, CLK-
OUT frequency
RSSi of last packet
0x25 RegPreambleMsb RegHopChannel 0x00 Preamble length, MSB FHSS start channel
0x26 RegPreambleLsb RegRxDataAddr 0x03
Preamble length, LSB
LoRa
TM
rx data pointer
0x27 RegSyncConfig 0x93 Sync Word Recognition control
0x28-
0x2F
RegSyncValue1-8 0x55
0x01
Sync Word bytes, 1 through 8
0x30 RegPacketConfig1 0x90 Packet mode settings
0x31 RegPacketConfig2 0x40 Packet mode settings
0x32 RegPayloadLength
RESERVED
0x40
Payload length setting
RESERVED
0x33 RegNodeAdrs 0x00 Node address
0x34 RegBroadcastAdrs 0x00 Broadcast address
0x35 RegFifoThresh 0x0F
0x8F
Fifo threshold, Tx start condi-
tion
0x36 RegSeqConfig1 0x00 Top level Sequencer settings
0x37 RegSeqConfig2 0x00 Top level Sequencer settings
0x38 RegTimerResol 0x00 Timer 1 and 2 resolution control
0x39 RegTimer1Coef 0xF5 Timer 1 setting
0x3A RegTimer2Coef 0x20 Timer 2 setting
0x3B RegImageCal 0x82
0x02
Image calibration engine con-
trol
0x3C RegTemp - Temperature Sensor value
0x3D RegLowBat 0x02 Low Battery Indicator Settings
0x3E RegIrqFlags1 0x80 Status register: PLL Lock state,
Timeout, RSSI
0x3F RegIrqFlags2
RESERVED
0x40 Status register: FIFO handling
flags, Low Battery
RESERVED
0x40 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3
0x41 RegDioMapping2 0x00 Mapping of pins DIO4 and DIO5, ClkOut frequency
0x42 RegVersion 0x11 Hope RF ID relating the silicon revision
0x44
RegPllHop Unused
0x2D Control the fast frequency hop-
ping mode
Unused
0x4B RegTcxo 0x09 TCXO or XTAL input setting